READ LATENCY REDUCTION FOR PARTIALLY-PROGRAMMED BLOCK OF NON-VOLATILE MEMORY

    公开(公告)号:US20210118510A1

    公开(公告)日:2021-04-22

    申请号:US17112401

    申请日:2020-12-04

    Abstract: Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent read latency. Determining in advance a wordline-specific pattern of wordline offsets associated with past unsuccessful reads in partially-programmed blocks allows read voltages to be proactively adjusted for vulnerable wordlines. Read voltages are restored for subsequent read operations.

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