公开(公告)号：US20160379715A1

公开(公告)日：2016-12-29

申请号：US14752817

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： David J. PELSTER ,  Yogesh B. WAKCHAURE ,  Xin GUO ,  Paul D. RUBY ,  Justin R. DAYACAP ,  Joseph F. DOLLER ,  Robert E. FRICKEY

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2216/20

Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Abstract translation: 提供了一种用于对非易失性存储器执行块擦除操作的装置，存储器控制器和方法。 产生用于执行块擦除操作的一部分的命令。 在执行命令后至少执行一次读或写操作。 响应于在执行至少一个读或写操作之后确定块擦除操作未完成，执行命令的附加实例。

公开(公告)号：US20210118510A1

公开(公告)日：2021-04-22

申请号：US17112401

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Joseph F. DOLLER ,  Kristopher H. GAEWSKY ,  Noah MEBANE

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/12

Abstract: Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent read latency. Determining in advance a wordline-specific pattern of wordline offsets associated with past unsuccessful reads in partially-programmed blocks allows read voltages to be proactively adjusted for vulnerable wordlines. Read voltages are restored for subsequent read operations.