公开(公告)号：US11237626B2

公开(公告)日：2022-02-01

申请号：US16662403

申请日：2019-10-24

Applicant: Intel Corporation

Inventor： Ravindra A. Babu ,  Sashank Ms ,  Satyanantha R. Musunuri ,  Sagar C. Pawar ,  Kalyan K. Kaipa ,  Vijayakumar Balakrishnan ,  Sameer Kp

IPC: G06T1/20 ,  G06T15/80 ,  G06F3/01 ,  G02B27/01

Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.

公开(公告)号：US10453430B2

公开(公告)日：2019-10-22

申请号：US15476992

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Sameer Kp ,  Selvakumar Panneer ,  Susanta Bhattacharjee ,  Mrinalini Attaluri

IPC: G09G5/39 ,  G06T1/60 ,  G06T1/20 ,  G09G5/36

Abstract: Methods, apparatus, and articles of manufacture to provide extended graphics processing capabilities are disclosed. A disclosed example method involves sending a display panel parameter to a shared library module. The display panel parameter is sent by a programmable driver interface in communication between the shared library module and a graphics hardware device driver. The shared library module includes a first graphics processing capability. The graphics hardware device driver includes a second graphics processing capability different from the first graphics processing capability. The example method also involves performing a render operation via the programmable driver interface on a frame buffer based on the first graphics processing capability. The first graphics processing capability is received at the programmable driver interface from the shared library module based on the display panel parameter. The frame buffer is output to a display.

公开(公告)号：US10134360B2

公开(公告)日：2018-11-20

申请号：US14552665

申请日：2014-11-25

Applicant: Intel Corporation

Inventor： Susanta Bhattacharjee ,  Sameer Kp

IPC: G09G5/02 ,  G09G5/06 ,  G09G5/36

Abstract: By converting a first color space to a second color space, using a two-dimensional lookup table in said second color space, and converting from said second color space to said first color space, it may be possible to use one or more two-dimensional lookup tables (LUTs) to do a task conventionally handled by three-dimensional lookup tables. This may reduce storage requirements and memory bandwidth requirements in some embodiments. In general a color pixel with N color components can be processed with n number of M dimensional LUT where M

公开(公告)号：US20180293760A1

公开(公告)日：2018-10-11

申请号：US15483701

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer Kp ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US20240134445A1

公开(公告)日：2024-04-25

申请号：US18497136

申请日：2023-10-29

Applicant: Intel Corporation

Inventor： Ravindra A. Babu ,  Sashank Ms ,  Satyanantha R. Musunuri ,  Sagar C. Pawar ,  Kalyan K. Kaipa ,  Vijayakumar Balakrishnan ,  Sameer Kp

IPC: G06F3/01 ,  G02B27/01 ,  G06T1/20

CPC classification number: G06F3/012 ,  G02B27/017 ,  G06F3/017 ,  G06T1/20 ,  G02B2027/0147 ,  G06F3/011

Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.

公开(公告)号：US11869119B2

公开(公告)日：2024-01-09

申请号：US17666193

申请日：2022-02-07

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer Kp ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T1/20 ,  G06T11/00 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US11348511B2

公开(公告)日：2022-05-31

申请号：US15090911

申请日：2016-04-05

Applicant: Intel Corporation

Inventor： Mallari C. Hanchate ,  Ganesh R. S.T. ,  Bharath Kumar ,  Sameer Kp

IPC: G09G3/20 ,  G09G3/34 ,  G06F3/14 ,  G09G5/00

Abstract: Two extended embedded Display Port displays may be enabled by using a single set of panel power sequencing (PPS) signals from a chipset to enable the two embedded Display Port panels. To enhance the user experience, the backlight module brightness is controlled by making use of a pin available on a system on a chip (SOC) and modification of drivers. This helps to save power when only one panel is used. When both panels are used simultaneously, power savings can be achieved by using backlight control signals.

公开(公告)号：US20200057490A1

公开(公告)日：2020-02-20

申请号：US16662403

申请日：2019-10-24

Applicant: Intel Corporation

Inventor： Ravindra A. Babu ,  Sashank Ms ,  Satyanantha R. Musunuri ,  Sagar C. Pawar ,  Kalyan K. Kaipa ,  Vijayakumar Balakrishnan ,  Sameer Kp

IPC: G06F3/01 ,  G02B27/01 ,  G06T1/20

Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.

公开(公告)号：US20190087983A1

公开(公告)日：2019-03-21

申请号：US16142866

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer Kp ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/60 ,  G06T15/00 ,  G06T1/20

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US20180307305A1

公开(公告)日：2018-10-25

申请号：US15494584

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Ravindra A. Babu ,  Sashank Sms Ms ,  Satyanantha R. Musunuri ,  Sagar C. Pawar ,  Kalyan K. Kaipa ,  Vijayakumar Balakrishnan ,  Sameer Kp

IPC: G06F3/01 ,  G06T1/20

CPC classification number: G06F3/012 ,  G06T1/20

Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.