公开(公告)号：US20190171269A1

公开(公告)日：2019-06-06

申请号：US16269551

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Naveen G ,  Bharath Kumar

IPC: G06F1/26 ,  G06F13/20 ,  G06F13/40

Abstract: Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.

公开(公告)号：US20160372027A1

公开(公告)日：2016-12-22

申请号：US15090911

申请日：2016-04-05

Applicant: Intel Corporation

Inventor： Mallari C. Hanchate ,  Ganesh R. S.T. ,  Bharath Kumar ,  Sameer KP

IPC: G09G3/20 ,  G09G3/34

CPC classification number: G09G3/2096 ,  G06F3/1431 ,  G09G3/3406 ,  G09G3/3614 ,  G09G5/006 ,  G09G2300/026 ,  G09G2320/064 ,  G09G2330/021 ,  G09G2330/026 ,  G09G2330/027 ,  G09G2370/10 ,  G09G2370/20

Abstract: Two extended embedded Display Port displays may be enabled by using a single set of panel power sequencing (PPS) signals from a chipset to enable the two embedded Display Port panels. To enhance the user experience, the backlight module brightness is controlled by making use of a pin available on a system on a chip (SOC) and modification of drivers. This helps to save power when only one panel is used. When both panels are used simultaneously, power savings can be achieved by using backlight control signals.

Abstract translation: 两个扩展的嵌入式显示端口显示器可以通过使用来自芯片组的一组面板电源排序（PPS）信号来启用两个嵌入式显示端口面板。 为了增强用户体验，通过利用芯片上的系统（SOC）上可用的引脚和驱动器的修改来控制背光模块的亮度。 这有助于在仅使用一个面板时节省电力。 当两个面板同时使用时，可以通过使用背光控制信号实现功率节省。

公开(公告)号：US11348511B2

公开(公告)日：2022-05-31

申请号：US15090911

申请日：2016-04-05

Applicant: Intel Corporation

Inventor： Mallari C. Hanchate ,  Ganesh R. S.T. ,  Bharath Kumar ,  Sameer Kp

IPC: G09G3/20 ,  G09G3/34 ,  G06F3/14 ,  G09G5/00

Abstract: Two extended embedded Display Port displays may be enabled by using a single set of panel power sequencing (PPS) signals from a chipset to enable the two embedded Display Port panels. To enhance the user experience, the backlight module brightness is controlled by making use of a pin available on a system on a chip (SOC) and modification of drivers. This helps to save power when only one panel is used. When both panels are used simultaneously, power savings can be achieved by using backlight control signals.

公开(公告)号：US11327547B2

公开(公告)日：2022-05-10

申请号：US17068704

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Naveen G ,  Bharath Kumar

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/3206

Abstract: Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.

公开(公告)号：US20210026432A1

公开(公告)日：2021-01-28

申请号：US17068704

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Naveen G ,  Bharath Kumar

IPC: G06F1/3206 ,  G06F1/26

Abstract: Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.

公开(公告)号：US10802565B2

公开(公告)日：2020-10-13

申请号：US16269551

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Naveen G ,  Bharath Kumar

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/3206

Abstract: Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.

公开(公告)号：US09891691B2

公开(公告)日：2018-02-13

申请号：US14039220

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Naveen Gopal Reddy ,  Bharath Kumar ,  Robert E. Gough

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3243 ,  Y02D10/152

Abstract: Methods and apparatus relating to reducing pin count requirements for implementation of interconnect idle state(s) are described. In one embodiment, logic receives a general purpose input signal on a signal pin of an Input/Output (I/O) complex logic in response to a control signal. An I/O device (e.g., coupled to the I/O complex logic) enters a low power consumption state in response to the control signal. The logic receives a wake signal on the signal pin of the I/O complex logic and the I/O device exits the low power consumption state in response to the wake signal. Other embodiments are also claimed and disclosed.