公开(公告)号：US20190108137A1

公开(公告)日：2019-04-11

申请号：US16211157

申请日：2018-12-05

Applicant: Intel Corporation

Inventor： Madhurima RAY ,  Sanjeev N. TRIKA

IPC: G06F12/121 ,  G06F12/0804

Abstract: An intelligent journal-aware caching manager for journaled data is provided. The caching manager ensures that data is not duplicated in a write-ahead-log (“journal”) and volatile cache memory (“cache”). The caching manager maintains first-in-first-out (“FIFO”) policy for the journal as needed and includes an alternate caching policy for non-journaled data.

公开(公告)号：US20190102262A1

公开(公告)日：2019-04-04

申请号：US15721625

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Vadim SUKHOMLINOV ,  Kshitij A. DOSHI ,  Tamir D. MUNAFO ,  Sanjeev N. TRIKA ,  Urvi PATEL ,  Rowel S. GARCIA

IPC: G06F11/14

Abstract: A storage controller performs continuous checkpointing. With continuous checkpointing, the information necessary for system rollback is continuously recorded without the need of a specific command. With the rollback information, the system can rollback or restore to any previous state up to a number of previous writes or up to an amount of data. The number of writes or the amount of data that can be restored are configurable.

公开(公告)号：US20190042152A1

公开(公告)日：2019-02-07

申请号：US15833955

申请日：2017-12-06

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA ,  Peng LI ,  Jawad B. KHAN ,  Myron LOEWEN

IPC: G06F3/06 ,  G06F11/07 ,  H04L29/08

Abstract: Examples include techniques for implementing a write transaction to two or more memory devices in a storage device. In some examples, the write transaction includes an atomic write transaction from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the storage device includes a storage controller to receive an atomic multimedia write transaction request to write first data and second data; cause the first data to be stored in a first memory device, and cause the second data to be stored in a second memory device, simultaneously and atomically.

公开(公告)号：US20170351452A1

公开(公告)日：2017-12-07

申请号：US15170879

申请日：2016-06-01

Applicant: INTEL CORPORATION

Inventor： James A. BOYD ,  John W. CARROLL ,  Sanjeev N. TRIKA

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/311 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7208

Abstract: In one embodiment, dynamic host memory buffer allocation in accordance with the present description includes sensing a level of activity of a memory or storage and dynamically allocating a portion of a host memory as a buffer to the non-volatile memory, as a function of a sensed level of activity of the non-volatile memory. Such dynamic allocation of host memory buffers as a function of sensed levels of activity, can improve the efficiency of the allocation of memory resources and improve system performance. Other aspects are described herein.

公开(公告)号：US20210311659A1

公开(公告)日：2021-10-07

申请号：US17350574

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Peng LI ,  Jawad B. KHAN ,  Sanjeev N. TRIKA

IPC: G06F3/06 ,  G06F12/1081

Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

公开(公告)号：US20200249980A1

公开(公告)日：2020-08-06

申请号：US16855139

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Bishwajit DUTTA ,  Sanjeev N. TRIKA ,  Anand S. RAMALINGAM ,  Pallav H. GALA

IPC: G06F9/46 ,  G06F9/54 ,  G06F9/48 ,  G06F3/06

Abstract: Examples include techniques for managing high priority (HP) and low priority (LP) write transaction requests by a storage device. An embodiment includes receiving, at a storage controller for a storage device, a write transaction request from a requestor to write data to one or more memory devices in the storage device. When the write transaction request is for a high priority (HP) write, coalescing the write data into a transaction buffer in a memory of the storage device, sending an acknowledgment for the write transaction request to the requestor, and writing the write data into the one or more memory devices. When the write transaction request is for a low priority (LP) write, writing the write data into the one or more memory devices, and then sending an acknowledgment for the write transaction request to the requestor.

公开(公告)号：US20190042571A1

公开(公告)日：2019-02-07

申请号：US15973428

申请日：2018-05-07

Applicant: Intel Corporation

Inventor： Peng LI ,  Sanjeev N. TRIKA

IPC: G06F17/30

Abstract: An update-insert (“upsert”) interface manages updates to key-value storage at a memory or storage device. An upsert token is used to store a key and data for a transform to update a previous value stored for a key-value pair. The upsert token processing includes an upsert command to generate the upsert token for an existing key-value pair and store the upsert token in one or more first non-volatile memory (NVM) devices maintained at a memory or storage device. A hash-to-physical (H2P) table or index stored in one or more second NVM devices of the memory or storage device is utilized to locate and read the data for the key and the data for the transform and coalesce the transform(s) into a current value for the key-value pair, thereby avoiding unnecessary read and write amplification when updating key-value storage.

公开(公告)号：US20190042111A1

公开(公告)日：2019-02-07

申请号：US15910476

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Rowel S. GARCIA ,  Sanjeev N. TRIKA ,  Jawad B. KHAN

IPC: G06F3/06 ,  G06F11/14

Abstract: Power-fail safe compression and dynamic capacity for a storage device in a computer system is provided. Metadata stored with each logical block in non-volatile memory in the storage device ensures that the mapping table may be recovered and stored in volatile memory for use by the computer system after power is restored to the computer system. In addition, the metadata ensures that a list of free logical block addresses written to the storage device prior to shutting down the computer system to provide access to the additional capacity that is available in the storage device by storing compressed data in the storage device may also be recovered.

公开(公告)号：US20180173420A1

公开(公告)日：2018-06-21

申请号：US15387600

申请日：2016-12-21

Applicant: INTEL CORPORATION

Inventor： Peng LI ,  William K. LUI ,  Sanjeev N. TRIKA

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F3/068 ,  G06F12/10 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and defragmentation operations. A non-volatile memory storage device has non-volatile memory and a main memory. A memory controller reads and writes to the non-volatile memory and maintains in the main memory a logical-to-physical address table indicating, for each logical address of a plurality of logical addresses, a physical address in the non-volatile memory having data for the logical address. The main memory maintains a validity table indicating for each physical address of a plurality of physical addresses in the non-volatile memory whether the physical address has valid data.

公开(公告)号：US20160170850A1

公开(公告)日：2016-06-16

申请号：US14566636

申请日：2014-12-10

Applicant: INTEL CORPORATION

Inventor： Dan J. WILLIAMS ,  Bryan E. VEAL ,  Annie FOONG ,  Sanjeev N. TRIKA

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/065 ,  G06F11/1474

Abstract: Provided are a computer program product, system, and method performing an atomic write operation across multiple storage devices. A determination is made of a plurality of storage devices on which to write data for a write operation. A tag is generated to uniquely identify the write operation. A write command is sent to each of the determined storage devices including the tag and write data to cause each of the storage devices to write the write data at the storage device. Each of the storage devices maintains a copy of a previous version of the data to be updated by the write operation. A revert command is sent with the tag to one of the storage devices to cause the storage device to restore the copy of the previous version of the write data at the storage device.

Abstract translation: 提供了一种在多个存储设备上执行原子写入操作的计算机程序产品，系统和方法。 确定写入用于写入操作的数据的多个存储装置。 生成标签以唯一地标识写入操作。 向每个确定的存储设备发送写入命令，包括标签和写入数据，以使每个存储设备将写入数据写入存储设备。 每个存储设备通过写入操作维护要更新的数据的先前版本的副本。 将标签发送到其中一个存储设备，以使存储设备在存储设备上还原先前版本的写入数据的副本。