公开(公告)号：US20190146936A1

公开(公告)日：2019-05-16

申请号：US16243936

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Dan J. WILLIAMS

IPC: G06F13/28 ,  G06F13/42 ,  G06F3/06

Abstract: Embodiments include a method to determine whether to dynamically remap an in-process update of a first page of memory to a second page of memory. When a dynamic remap is determined, the method causes a pause of the in-process update to the first page of memory by one or more bridges, draining of in-process direct memory access (DMA) operations, and redirecting the update to the second page of memory.

公开(公告)号：US20160170850A1

公开(公告)日：2016-06-16

申请号：US14566636

申请日：2014-12-10

Applicant: INTEL CORPORATION

Inventor： Dan J. WILLIAMS ,  Bryan E. VEAL ,  Annie FOONG ,  Sanjeev N. TRIKA

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/065 ,  G06F11/1474

Abstract: Provided are a computer program product, system, and method performing an atomic write operation across multiple storage devices. A determination is made of a plurality of storage devices on which to write data for a write operation. A tag is generated to uniquely identify the write operation. A write command is sent to each of the determined storage devices including the tag and write data to cause each of the storage devices to write the write data at the storage device. Each of the storage devices maintains a copy of a previous version of the data to be updated by the write operation. A revert command is sent with the tag to one of the storage devices to cause the storage device to restore the copy of the previous version of the write data at the storage device.

Abstract translation: 提供了一种在多个存储设备上执行原子写入操作的计算机程序产品，系统和方法。 确定写入用于写入操作的数据的多个存储装置。 生成标签以唯一地标识写入操作。 向每个确定的存储设备发送写入命令，包括标签和写入数据，以使每个存储设备将写入数据写入存储设备。 每个存储设备通过写入操作维护要更新的数据的先前版本的副本。 将标签发送到其中一个存储设备，以使存储设备在存储设备上还原先前版本的写入数据的副本。

公开(公告)号：US20220114086A1

公开(公告)日：2022-04-14

申请号：US17560007

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Chace A. CLARK ,  James A. BOYD ,  Chet R. DOUGLAS ,  Andrew M. RUDOFF ,  Dan J. WILLIAMS

IPC: G06F12/02

Abstract: Examples include techniques to expand system memory via use of available device memory. Circuitry at a device coupled to a host device partitions a portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload. The partitioned portion of memory capacity is reported to the host device as being available for use as a portion of system memory. An indication from the host device is received if the portion of memory capacity has been identified for use as a first portion of pooled system memory. The circuitry to monitor usage of the memory capacity used by the compute circuitry to execute the workload to decide whether to place a request to the host device to reclaim the memory capacity from the first portion of pooled system memory.

公开(公告)号：US20180089099A1

公开(公告)日：2018-03-29

申请号：US15280965

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Ashok RAJ ,  Sivakumar RADHAKRISHNAN ,  Dan J. WILLIAMS ,  Vishal VERMA ,  Narayan RANGANATHAN ,  Chet R. DOUGLAS

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/65

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.