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公开(公告)号:US20210223979A1
公开(公告)日:2021-07-22
申请号:US17203174
申请日:2021-03-16
Applicant: Intel Corporation
Inventor: Peng LI , Sanjeev N. TRIKA , David C. ESTRADA
IPC: G06F3/06
Abstract: On-SSD-copy using Copy-On-Write (COW) techniques track indirection updates to the copied data without duplicating the data. In one example, a method involves receiving a copy command to copy data from a source LBA to a destination LBA. An entry in a logical-to-physical (L2P) table corresponding to the destination LBA is updated to refer to the same physical address as the source LBA's entry in the L2P table. Flags in the L2P table are updated to indicate that more than one LBA refers to the same physical address. After updating the L2P table and before copying the data, a token is stored to the storage device. After storing the token, but before copying the data, an acknowledgement can be sent to the host to indicate the copy command is complete. A subsequent write to either the source or destination LBAs trigger a copy of the data.
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公开(公告)号:US20210193552A1
公开(公告)日:2021-06-24
申请号:US16721809
申请日:2019-12-19
Applicant: Intel Corporation
Inventor: Zhimin WAN , Jin YANG , Chia-Pin CHIU , Peng LI , Deepak GOYAL
IPC: H01L23/367 , H01L25/18 , H01L25/065 , H01L23/31
Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.
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公开(公告)号:US20190043778A1
公开(公告)日:2019-02-07
申请号:US16061324
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Zhizhong TANG , Shinobu KOURAKATA , Kazuo OGATA , Paul R. START , Syadwad JIAN , William Nicholas LABANOK , Wei HU , Peng LI , Douglas R. YOUNG , Gregory S. CONSTABLE , John J. Beatty , Pardeep K. BHATTI , Luke J. GARNER , Aravindha R. ANTONISWAMY
IPC: H01L23/367 , H01L21/48 , H01L25/065
Abstract: Embodiments are generally directed to a swaging process for complex integrated heat spreaders. An embodiment of an integrated heat spreader includes components, each of the components including one or more swage points; and a multiple swage joints, each swage joint including a swage pin joining two or more components, wherein components are joined into a single integrated heat spreader unit by the swage joints.
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公开(公告)号:US20190324683A1
公开(公告)日:2019-10-24
申请号:US16457982
申请日:2019-06-29
Applicant: Intel Corporation
Inventor: Peng LI , Jawad B. KHAN , Sanjeev N. TRIKA
IPC: G06F3/06 , G06F12/1081
Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.
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公开(公告)号:US20190004768A1
公开(公告)日:2019-01-03
申请号:US15636974
申请日:2017-06-29
Applicant: Intel Corporation
Inventor: Peng LI , Jawad B. KHAN , Sanjeev TRIKA
Abstract: One embodiment provides a storage device. The storage device includes a storage I/O (input/output) logic and a storage device controller. The storage I/O logic is to couple the storage device to a host device, the storage I/O logic to receive a sort-merge command the host device. The a storage device controller is to identify a level N SSTable (sorted string table) file, a corresponding level N index file, a first level N+1 SSTable file and a corresponding first level N+1 index file, in response to the sort-merge command to be received from the host device. The storage device controller is further to perform a sort-merge of the level N SSTable file and the first level N+1 SSTable file to produce a first level N+1 output SSTable file and a first level N+1 output SSTable index file. The level N SSTable file includes at least one level N key-value (KV) pair. The level N+1 SSTable file includes at least one level N+1 key-value (KV) pair. The sort-merge command includes a level N SSTable file index, a value corresponding to a number of SSTable files included in level N+1 and a level N+1 start SSTable file index. The identifying is based, at least in part, on the level N SSTable file index and the level N+1 start SSTable file index.
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6.
公开(公告)号:US20180267706A1
公开(公告)日:2018-09-20
申请号:US15460043
申请日:2017-03-15
Applicant: INTEL CORPORATION
Inventor: Peng LI , Sanjeev N. TRIKA
Abstract: Provided are a computer program product, system and method for managing read/write operations in a hybrid memory device system. Determinations are made of an available physical address in a first memory device for a data block to allocate for metadata for a file or directory in a file system and a first logical address corresponding to the available physical address in a first range of logical addresses. Determinations are made of an available physical address in a second memory device for a data block to allocate for the file or directory in the file system and a second logical address corresponding to the available physical address in the second memory device in a second range of logical addresses. The second logical address is used to access the data block allocated to the file or directory in the file system.
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公开(公告)号:US20180189000A1
公开(公告)日:2018-07-05
申请号:US15394453
申请日:2016-12-29
Applicant: INTEL CORPORATION
Inventor: Peng LI , Sanjeev N. TRIKA
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0608 , G06F3/0688 , G06F12/0246 , G06F2212/1044 , G06F2212/401 , G06F2212/7201
Abstract: Provided are an apparatus, method, and system for logical block address to physical block address (L2P) compression. In response to a physical block address (PBA) of a first indirection unit (IU) among a plurality of IUs in a compression unit being updated, it is determined whether IU data of the plurality of IUs is compressible. In response to determining that the IU data is compressible, one or more contiguous IU groups in the compression unit that are compressible are identified based on corresponding PBAs and, then, a compression unit descriptor and PBAs for unique IUs of the plurality of IUs are written into the compression unit. In response to determining that the IU data is incompressible, a flag indicating that IU data is incompressible, PBAs for some of the IUs, and a pointer to PBAs of remaining IUs are written into the compression unit.
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8.
公开(公告)号:US20180173418A1
公开(公告)日:2018-06-21
申请号:US15385791
申请日:2016-12-20
Applicant: INTEL CORPORATION
Inventor: Peng LI , Anand S. RAMALINGAM , Jawad B. KHAN , William K. LUI , Divya NARAYANAN , Sanjeev N. TRIKA
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0655 , G06F3/0656 , G06F3/0659 , G06F3/0688
Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.
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公开(公告)号:US20220199482A1
公开(公告)日:2022-06-23
申请号:US17131671
申请日:2020-12-22
Applicant: Intel Corporation
Inventor: Chia-Pin CHIU , Zhimin WAN , Peng LI , Deepak GOYAL
IPC: H01L23/367 , H01L23/40 , H01L23/38
Abstract: Embodiments disclosed herein include thermoelectric cooling (TEC) dies for multi-chip packages. In an embodiment, a TEC die comprises a glass substrate and an array of N-type semiconductor vias and P-type semiconductor vias through the glass substrate. In an embodiment, conductive traces are over the glass substrate, and individual ones of the conductive traces connect an individual one of the N-type semiconductor vias to an individual one of the P-type semiconductor vias.
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公开(公告)号:US20190227884A1
公开(公告)日:2019-07-25
申请号:US16370644
申请日:2019-03-29
Applicant: Intel Corporation
Inventor: Peng LI , David J. PELSTER , Gamil CAIN , Ryan J. NORTON
Abstract: A solid state drive (SSD) includes a nonvolatile memory array and a cache memory. The nonvolatile memory array has an encrypted integrated memory buffer (IMB) space. The cache memory has a decrypted copy of the IMB and an encrypted backup copy of the IMB. In power loss recovery (PLR) after a power loss imminent (PLI) event, the SSD can determine whether to recover the unencrypted copy of the IMB or the backup encrypted copy. The backup encrypted copy can reduce the risk of loss of data in the IMB in the event that multiple PLI events occur and a corrupted copy of the IMB is used to overwrite the IMB in the nonvolatile memory during a previous PLR.
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