公开(公告)号：US20180287953A1

公开(公告)日：2018-10-04

申请号：US15531692

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Albert S. CHENG ,  Michael A. PARKER ,  Thomas D. LOVETT ,  Steven F. HOOVER

IPC: H04L12/863

Abstract: Apparatuses, methods and storage medium associated with the placement of data packets in one or more queues of a switch are described herein. In embodiments, the switch may include a plurality of virtual lane (VL) queues (VLQs) and a plurality of generic queues (GQs). A queue manager may be configured to selectively place a packet of a particular VL in a corresponding VLQ or a GQ. Other embodiments may be described and/or claimed.

公开(公告)号：US20170339106A1

公开(公告)日：2017-11-23

申请号：US15531168

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： Todd M. RIMMER ,  Thomas D. LOVETT ,  Alberto J. MUNOZ

IPC: H04L29/06 ,  H04L12/823 ,  H04L12/947 ,  H04L29/08

CPC classification number: H04L63/0236 ,  H04L12/6418 ,  H04L47/32 ,  H04L49/25 ,  H04L63/166 ,  H04L67/141

Abstract: Technologies for fabric security include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A managed network device enables a port and, while enabling the port, securely determines the node type of the link partner coupled to the port. If the link partner is a computing node, management access is not allowed at the port. The managed network device may allow management access at certain predefined ports, which may be connected to one of more management nodes. Management access may be allowed for additional ports in response to management messages received from the management nodes. The managed network device may check and verify data packet headers received from a compute node at each port. The managed network device may rate-limit management messages received from a compute node at each port. Other embodiments are described and claimed.

公开(公告)号：US20180287963A1

公开(公告)日：2018-10-04

申请号：US15531643

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. CHENG ,  Thomas D. LOVETT ,  Michael A. PARKER ,  Steven F. HOOVER ,  Gregory J. HUBBARD

IPC: H04L12/933 ,  H04L12/937

CPC classification number: H04L49/101 ,  H04L49/107 ,  H04L49/109 ,  H04L49/254

Abstract: Apparatuses, methods and storage media associated with multiple multi-drop buses in a switch are provided herein. In some embodiments, the switch may include a multi-drop row bus to transmit a plurality of frames in a row dimension of the matrix switch and a multi-drop column bus to transmit the plurality of frames in a column dimension of the matrix switch. The switch may further include an input port to receive the plurality of frames and an output port to output the plurality of frames from the matrix switch. Other embodiments may be described and/or claimed.

公开(公告)号：US20170351294A1

公开(公告)日：2017-12-07

申请号：US15531193

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： Thomas D. LOVETT

IPC: G06F1/10 ,  G06F1/12

Abstract: Technologies for synchronized sampling of counters include a computing device to determine a global clock to which the computing device and a plurality of other computing devices are to be synchronized. The computing device receives a request to sample a counter of the computing device from an administration server and records a state of the counter based on the global clock in response to receiving the request.

公开(公告)号：US20170339071A1

公开(公告)日：2017-11-23

申请号：US15531688

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. CHENG ,  Thomas D. LOVETT ,  Michael A. PARKER

IPC: H04L12/947 ,  H04L12/835 ,  H04L12/741 ,  H04L12/801 ,  H04L12/935 ,  H04L12/933

Abstract: Apparatuses, methods and storage medium associated with routing data in a switch are provided. In embodiments, the switch may include route lookup circuitry determine a first set of output ports that are available to send a data packet to a destination node. The lookup circuitry may further select, based on respective congestion levels associated with the first set of output ports, a plurality of output ports for a second set of output ports from the first set of output ports. An input queue of the switch may buffer the data packet and route information associated with the second set of output ports. The switch may further include route selection circuitry to select a destination output port from the second set of output ports, based on updated congestion levels associated with the output ports of the second set of output ports. Other embodiments may be described and/or claimed.

公开(公告)号：US20170295112A1

公开(公告)日：2017-10-12

申请号：US15531694

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. CHENG ,  Thomas D. LOVETT ,  Michael S. PARKER ,  Steven F. HOOVER

IPC: H04L12/935 ,  H04L12/937

CPC classification number: H04L49/3036 ,  H04L12/6418 ,  H04L49/101 ,  H04L49/103 ,  H04L49/254 ,  H04L49/505 ,  H04L49/9036

Abstract: Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.