公开(公告)号：US20230315501A1

公开(公告)日：2023-10-05

申请号：US17711770

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Rangeen Basu Roy Chowdhury ,  Matthew C. Merten ,  Jason M. Agron ,  Tyler N. Sondag ,  Gregory A. Woods

IPC: G06F9/455

CPC classification number: G06F9/4552 ,  G06F9/45525

Abstract: Systems, methods, and devices for original code emulation for performance monitoring is provided. A system may memory to store instructions. A processor may implement an instruction converter in hardware or software to convert the instructions to translated code. Specifically, the instruction converter receives the instructions and translates the stored instructions into the translated code that includes one or more indexed instructions. The one or more indexed instructions include a field indicating a number of branches in the stored instructions that are taken in the translated code.

公开(公告)号：US10761849B2

公开(公告)日：2020-09-01

申请号：US15273163

申请日：2016-09-22

Applicant: Intel Corporation

Inventor： Ching-Tsun Chou ,  Oleg Margulis ,  Tyler N. Sondag

IPC: G06F9/30

Abstract: A processor of an aspect includes a decode unit to decode a prior instruction that is to have at least a first context, and a subsequent instruction. The subsequent instruction is to be after the prior instruction in original program order. The decode unit is to use the first context of the prior instruction to determine a second context for the subsequent instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the subsequent instruction based at least in part on the second context. Other processors, methods, systems, and machine-readable medium are also disclosed.

公开(公告)号：US10324724B2

公开(公告)日：2019-06-18

申请号：US14971904

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Patrick P. Lai ,  Tyler N. Sondag ,  Sebastian Winkel ,  Polychronis Xekalakis ,  Ethan Schuchman ,  Jayesh Iyer

IPC: G06F9/30

Abstract: Methods and apparatuses relating to a fusion manager to fuse instructions are described. In one embodiment, a hardware processor includes a hardware binary translator to translate an instruction stream into a translated instruction stream, a hardware fusion manager to fuse multiple instructions of the translated instruction stream into a single fused instruction, a hardware decode unit to decode the single fused instruction into a decoded, single fused instruction, and a hardware execution unit to execute the decoded, single fused instruction.

公开(公告)号：US10083033B2

公开(公告)日：2018-09-25

申请号：US14643855

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Sebastian Winkel ,  Girish Venkatasubramanian ,  Tyler N. Sondag ,  Rolf Kassa

IPC: G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863

Abstract: A method and apparatus are described for efficient register reclamation. For example, one embodiment of an apparatus comprises: single usage detection and tagging logic to examine a sequence of instructions to detect logical registers used by the sequence of instructions that have a single use and to tag an instruction as a single usage instruction if the instruction is a consumer of a logical register that has a single use; an allocator to allocate processor resources to execute the sequence of instructions, the processor resources including physical registers mapped to logical registers to execute the sequence of instructions; and register reclamation logic to free up a logical to physical mapping of a single use register in response to detecting the tag provided by the instruction tagging logic.

公开(公告)号：US20180081684A1

公开(公告)日：2018-03-22

申请号：US15273163

申请日：2016-09-22

Applicant: Intel Corporation

Inventor： Ching-Tsun Chou ,  Oleg Margulis ,  Tyler N. Sondag

IPC: G06F9/30

Abstract: A processor of an aspect includes a decode unit to decode a prior instruction that is to have at least a first context, and a subsequent instruction. The subsequent instruction is to be after the prior instruction in original program order. The decode unit is to use the first context of the prior instruction to determine a second context for the subsequent instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the subsequent instruction based at least in part on the second context. Other processors, methods, systems, and machine-readable medium are also disclosed.

公开(公告)号：US20170192788A1

公开(公告)日：2017-07-06

申请号：US14988298

申请日：2016-01-05

Applicant: Intel Corporation

Inventor： Oleg Margulis ,  Jason M. Agron ,  Tyler N. Sondag

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/30138 ,  G06F9/30174 ,  G06F9/4552

Abstract: A processing system implementing techniques for binary translation support using processor instruction prefixes is provided. In one embodiment, the processing system includes a register bank having a plurality of registers to store data for use in executing instructions and a processor core coupled to the register bank. An instruction to be executed by the processor core is received. The instruction is associated with a binary translator operation to translate input instruction sequences to output instruction sequences. An opcode prefix referencing an extended register of the plurality of registers to be used during the binary translator operation. The extended register preserves a source register value of the plurality of registers.

公开(公告)号：US20160266905A1

公开(公告)日：2016-09-15

申请号：US14644130

申请日：2015-03-10

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Ethan Schuchman ,  Rainer Theuer ,  Gregor Stellpflug ,  Tyler N. Sondag

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/4552 ,  G06F9/5027 ,  G06F2209/5018

Abstract: Methods and apparatuses relating to assigning a logical thread to a physical thread. In one embodiment, an apparatus includes a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction, assigning a logical thread for the translated instruction, and providing a thread map hint for the translated instruction; and a hardware scheduler to assign a physical thread of the hardware processor to execute the logical thread based on the thread map hint.

Abstract translation: 将逻辑线程分配给物理线程的方法和装置。 在一个实施例中，一种装置包括数据存储装置，其存储当由硬件处理器执行时使得硬件处理器执行以下操作的代码：将指令转换为转换的指令，为翻译的指令分配逻辑线程， 线程图提示翻译指令; 以及硬件调度器，用于分配硬件处理器的物理线程以基于线程图提示来执行逻辑线程。