公开(公告)号：US10474471B2

公开(公告)日：2019-11-12

申请号：US15131425

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Klaus Danne ,  Cristiano L. Pereira ,  Gilles A. Pokam ,  Rolf Kassa ,  Shiliang Hu ,  Tim Kranich

IPC: G06F9/44 ,  G06F9/38 ,  G06F9/455 ,  G06F11/30 ,  G06F11/36 ,  G06F11/34 ,  G06F9/30 ,  G06F9/52

Abstract: One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.

公开(公告)号：US20160299760A1

公开(公告)日：2016-10-13

申请号：US15131425

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Klaus Danne ,  Cristiano L. Pereira ,  Gilles A. Pokam ,  Rolf Kassa ,  Shiliang Hu ,  Tim Kranich

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/44 ,  G06F9/3005 ,  G06F9/30072 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/455 ,  G06F9/52 ,  G06F11/30 ,  G06F11/3414 ,  G06F11/3476 ,  G06F11/36 ,  G06F11/3664 ,  G06F11/3688 ,  G06F2201/815 ,  G06F2201/825 ,  G06F2201/865

Abstract: One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.

Abstract translation: 一个或多个实施例可以提供用于执行重放的方法。 该方法包括启动程序的执行，程序具有多组指令，并且每组指令具有多个指令块。 该方法还包括通过在处理器上执行的虚拟机单元截取在执行之前块数量的指令。 该方法还包括通过在处理器上执行的重播模块确定该块是否是活动块，并且响应于该块作为活动块来执行该指令。

公开(公告)号：US20210374069A1

公开(公告)日：2021-12-02

申请号：US17404770

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14 ,  G06F12/0864

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US09128781B2

公开(公告)日：2015-09-08

申请号：US13729718

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Tim Kranich ,  Gilles A. Pokam ,  Justin E. Gottschlich ,  Klaus Danne ,  Rolf Kassa ,  Shiliang Hu ,  Cristiano L. Pereira

IPC: G06F9/52 ,  G06F11/36

CPC classification number: G06F9/526 ,  G06F11/3404 ,  G06F11/3409 ,  G06F11/3471 ,  G06F11/36 ,  G06F11/3636

Abstract: A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.

Abstract translation: 处理器包括执行第一软件线程的第一核，执行第二软件线程的第二核和共享存储器存取监视和记录逻辑。 该逻辑包括存储器访问监视器逻辑，以监视第一线程对存储器的访问，记录被监视的访问的存储器地址，以及检测与其他线程相关的记录存储器地址的数据比赛。 逻辑包括块生成逻辑是生成块来表示第一个线程的提交执行。 每个块都包括执行和提交的第一个线程的一些指令和一个时间戳。 块生成逻辑是通过存储器访问监视器逻辑来检测数据竞赛来停止生成当前块。 块缓冲区是临时存储块，直到块被从处理器传出。

公开(公告)号：US09317297B2

公开(公告)日：2016-04-19

申请号：US13629131

申请日：2012-09-27

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Klaus Danne ,  Cristiano L. Pereira ,  Gilles A. Pokam ,  Rolf Kassa ,  Shiliang Hu ,  Tim Kranich

IPC: G06F9/44 ,  G06F9/38 ,  G06F9/455 ,  G06F11/30 ,  G06F11/36 ,  G06F11/34 ,  G06F9/52

CPC classification number: G06F9/3005 ,  G06F9/30072 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/44 ,  G06F9/455 ,  G06F9/52 ,  G06F11/30 ,  G06F11/3414 ,  G06F11/3476 ,  G06F11/36 ,  G06F11/3664 ,  G06F11/3688 ,  G06F2201/815 ,  G06F2201/825 ,  G06F2201/865

Abstract: Embodiments may provide a method for performing a replay of a previous execution of a program. The method includes generating an order of recorded chunks of instructions across a plurality of recorded threads based, at least in part, on log files generated from the previous execution of the program. The method includes initiating execution of the program, the executing program having a plurality of threads, each thread having a number of chunks of instructions. The method includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk before the instruction is executed. The method includes determining, by a replay module executing on the processor, that the chunk is an active chunk if the chunk is currently in line for execution according to the order of recorded chunks, and responsive to a determination that the chunk is the active chunk, executing the instruction.

Abstract translation: 实施例可以提供用于执行程序的先前执行的重放的方法。 该方法包括至少部分地基于从先前执行的程序生成的日志文件来生成跨多个记录的线程的所记录的指令块的顺序。 该方法包括启动程序的执行，执行程序具有多个线程，每个线程具有多个指令块。 该方法包括在执行指令之前由在处理器上执行的虚拟机单元截取块的指令。 该方法包括通过在处理器上执行的重放模块来确定，如果该组块当前正在与行记录在一起以便执行，则根据所记录的块的顺序来确定该块是活动块，并且响应于该块是活动块的确定 执行指令。

公开(公告)号：US10445245B2

公开(公告)日：2019-10-15

申请号：US15384067

申请日：2016-12-19

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14 ,  G06F12/0864

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US10445244B2

公开(公告)日：2019-10-15

申请号：US15384054

申请日：2016-12-19

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14 ,  G06F12/0864

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US10394561B2

公开(公告)日：2019-08-27

申请号：US15297885

申请日：2016-10-19

Applicant: INTEL CORPORATION

Inventor： Nathan D. Dautenhahn ,  Justin Gottschlich ,  Gilles Pokam ,  Cristiano Pereira ,  Shiliang Hu ,  Klaus Danne ,  Rolf Kassa

IPC: G06F9/45 ,  G06F9/30 ,  G06F11/07 ,  G06F9/38 ,  G06F11/14 ,  G06F11/36 ,  G06F9/52

Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

公开(公告)号：US09934155B2

公开(公告)日：2018-04-03

申请号：US13722485

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/10 ,  G06F12/14 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/109

CPC classification number: G06F12/1009 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/152 ,  G06F2212/6032 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/68

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US20200242046A1

公开(公告)日：2020-07-30

申请号：US16560213

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/1009 ,  G06F12/0864 ,  G06F12/14 ,  G06F12/1027

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.