公开(公告)号：US20230138386A1

公开(公告)日：2023-05-04

申请号：US18085258

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： ANDREW P. COLLINS ,  DIGVIJAY A. RAORANE ,  WILFRED GOMES ,  RAVINDRANATH V. MAHAJAN ,  SUJIT SHARAN

IPC: H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L21/50

Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.

公开(公告)号：US20200312833A1

公开(公告)日：2020-10-01

申请号：US16902123

申请日：2020-06-15

Applicant: INTEL CORPORATION

Inventor： WILFRED GOMES ,  MARK T. BOHR ,  RAJESH KUMAR ,  ROBERT L. SANKMAN ,  RAVINDRANATH V. MAHAJAN ,  WESLEY D. MC CULLOUGH

IPC: H01L25/18 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522 ,  H01L25/16 ,  H01L25/065

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US20190206798A1

公开(公告)日：2019-07-04

申请号：US15857752

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： ANDREW P. COLLINS ,  DIGVIJAY A. RAORANE ,  WILFRED GOMES ,  RAVINDRANATH V. MAHAJAN ,  SUJIT SHARAN

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/0655

Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.