-
公开(公告)号:US20230138386A1
公开(公告)日:2023-05-04
申请号:US18085258
申请日:2022-12-20
Applicant: Intel Corporation
Inventor: ANDREW P. COLLINS , DIGVIJAY A. RAORANE , WILFRED GOMES , RAVINDRANATH V. MAHAJAN , SUJIT SHARAN
IPC: H01L23/538 , H01L23/48 , H01L25/065 , H01L21/48 , H01L21/50
Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.
-
公开(公告)号:US20160172320A1
公开(公告)日:2016-06-16
申请号:US14566185
申请日:2014-12-10
Applicant: Intel Corporation
Inventor: RAJASEKARAN SWAMINATHAN , RAVINDRANATH V. MAHAJAN
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L23/49811 , H01L23/49827 , H01L24/11 , H01L24/16 , H01L24/742 , H01L24/75 , H01L24/81 , H01L2224/1132 , H01L2224/11418 , H01L2224/1147 , H01L2224/11474 , H01L2224/1148 , H01L2224/11849 , H01L2224/13017 , H01L2224/13022 , H01L2224/13023 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/13294 , H01L2224/133 , H01L2224/13311 , H01L2224/13316 , H01L2224/13355 , H01L2224/13357 , H01L2224/1336 , H01L2224/13387 , H01L2224/13411 , H01L2224/13447 , H01L2224/16227 , H01L2224/16237 , H01L2224/16503 , H01L2224/75264 , H01L2224/81192 , H01L2224/81193 , H01L2224/81222 , H01L2224/81409 , H01L2224/81439 , H01L2224/81444 , H01L2224/81455 , H01L2224/81464 , H01L2224/8181 , H01L2224/81815 , H01L2924/01026 , H01L2924/01027 , H01L2924/01028 , H01L2924/01322 , H01L2924/014 , H01L2924/3511 , H01L2924/3512 , H01L2924/35121 , H05K3/3436 , H05K3/3484 , H05K3/3494 , H05K2201/0341 , H05K2201/083 , H05K2201/10674 , H05K2203/104 , Y02P70/613 , H01L2924/01082 , H01L2924/0105 , H01L2924/01083 , H01L2924/01047 , H01L2924/01029 , H01L2924/00014 , H01L2924/00012 , H01L2924/05381 , H01L2924/053 , H01L2924/0532 , H01L2924/01056
Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.
-
公开(公告)号:US20200312833A1
公开(公告)日:2020-10-01
申请号:US16902123
申请日:2020-06-15
Applicant: INTEL CORPORATION
Inventor: WILFRED GOMES , MARK T. BOHR , RAJESH KUMAR , ROBERT L. SANKMAN , RAVINDRANATH V. MAHAJAN , WESLEY D. MC CULLOUGH
IPC: H01L25/18 , H01L23/48 , H01L25/00 , H01L23/00 , H01L23/538 , H01L23/522 , H01L25/16 , H01L25/065
Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
-
公开(公告)号:US20190206798A1
公开(公告)日:2019-07-04
申请号:US15857752
申请日:2017-12-29
Applicant: Intel Corporation
Inventor: ANDREW P. COLLINS , DIGVIJAY A. RAORANE , WILFRED GOMES , RAVINDRANATH V. MAHAJAN , SUJIT SHARAN
IPC: H01L23/538 , H01L21/50 , H01L21/48
CPC classification number: H01L23/5386 , H01L23/48 , H01L23/5385 , H01L23/66 , H01L25/0652 , H01L25/0655
Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.
-
公开(公告)号:US20160379951A9
公开(公告)日:2016-12-29
申请号:US14566185
申请日:2014-12-10
Applicant: Intel Corporation
Inventor: RAJASEKARAN SWAMINATHAN , RAVINDRANATH V. MAHAJAN
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L23/49811 , H01L23/49827 , H01L24/11 , H01L24/16 , H01L24/742 , H01L24/75 , H01L24/81 , H01L2224/1132 , H01L2224/11418 , H01L2224/1147 , H01L2224/11474 , H01L2224/1148 , H01L2224/11849 , H01L2224/13017 , H01L2224/13022 , H01L2224/13023 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/13294 , H01L2224/133 , H01L2224/13311 , H01L2224/13316 , H01L2224/13355 , H01L2224/13357 , H01L2224/1336 , H01L2224/13387 , H01L2224/13411 , H01L2224/13447 , H01L2224/16227 , H01L2224/16237 , H01L2224/16503 , H01L2224/75264 , H01L2224/81192 , H01L2224/81193 , H01L2224/81222 , H01L2224/81409 , H01L2224/81439 , H01L2224/81444 , H01L2224/81455 , H01L2224/81464 , H01L2224/8181 , H01L2224/81815 , H01L2924/01026 , H01L2924/01027 , H01L2924/01028 , H01L2924/01322 , H01L2924/014 , H01L2924/3511 , H01L2924/3512 , H01L2924/35121 , H05K3/3436 , H05K3/3484 , H05K3/3494 , H05K2201/0341 , H05K2201/083 , H05K2201/10674 , H05K2203/104 , Y02P70/613 , H01L2924/01082 , H01L2924/0105 , H01L2924/01083 , H01L2924/01047 , H01L2924/01029 , H01L2924/00014 , H01L2924/00012 , H01L2924/05381 , H01L2924/053 , H01L2924/0532 , H01L2924/01056
Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.
Abstract translation: 本公开涉及制造微电子封装的领域,其中分布在焊膏内的磁性颗粒可用于形成磁性金属间化合物互连。 金属间化合物互连可以暴露于磁场,磁场可以将焊料材料加热到回流温度,以附接包括微电子封装的微电子部件。
-
-
-
-