-
1.
公开(公告)号:US20180068926A1
公开(公告)日:2018-03-08
申请号:US15553932
申请日:2015-03-27
Applicant: INTEL CORPORATION
Inventor: JAN KRAJNIAK , TANNAZ HARIRCHIAN , KELLY P. LOFGREEN , JAMES C. MATAYABAS, Jr. , NACHIKET R. RARAVIKAR , ROBERT L. SANKMAN
IPC: H01L23/427 , H01L23/373 , H01L21/77
Abstract: Embodiments of the present disclosure describe an energy storage material for thermal management and associated techniques and configurations. In one embodiment, an energy storage material may include an organic matrix and a solid-solid phase change material dispersed in the organic matrix, the solid-solid phase change material to change crystalline structure and absorb heat while remaining a solid at a threshold temperature associated with operation of an integrated circuit (IC) die. Other embodiments may be described and/or claimed.
-
公开(公告)号:US20200243956A1
公开(公告)日:2020-07-30
申请号:US16258573
申请日:2019-01-26
Applicant: INTEL CORPORATION
Inventor: ZHENGUO JIANG , OMKAR KARHADE , SRICHAITRA CHAVALI , ZHICHAO ZHANG , JIMIN YAO , STEPHEN SMITH , XIAOQIAN LI , ROBERT L. SANKMAN
Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.
-
公开(公告)号:US20180372952A1
公开(公告)日:2018-12-27
申请号:US15979382
申请日:2018-05-14
Applicant: Intel Corporation
Inventor: ZHICHAO ZHANG , KEMAL AYGUN , ROBERT L. SANKMAN
CPC classification number: G02B6/12004 , G02B6/4257 , G02B6/428 , G02B6/4295 , G02B6/43 , G02B2006/12121 , G02B2006/12142 , G02B2006/12147
Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.
-
公开(公告)号:US20180226334A1
公开(公告)日:2018-08-09
申请号:US15748106
申请日:2015-08-27
Applicant: INTEL CORPORATION
Inventor: ROBERT L. SANKMAN , ALLAN A. OVROM, III , ROBERT STARKSTON , OREN ARAD
IPC: H01L23/498 , H01L23/538 , H01L23/00
CPC classification number: H01L23/49894 , H01L23/49816 , H01L23/5383 , H01L24/00 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73253 , H01L2224/73267 , H01L2224/92244
Abstract: Embodiments herein may relate to a package that includes a package substrate with a first die on a first side of the package substrate and a second die on a second side of the package substrate. Solder balls may be coupled with the second side of the package substrate and the second die such that the solder balls are approximately coplanar. Other embodiments may be described and/or claimed
-
公开(公告)号:US20200312833A1
公开(公告)日:2020-10-01
申请号:US16902123
申请日:2020-06-15
Applicant: INTEL CORPORATION
Inventor: WILFRED GOMES , MARK T. BOHR , RAJESH KUMAR , ROBERT L. SANKMAN , RAVINDRANATH V. MAHAJAN , WESLEY D. MC CULLOUGH
IPC: H01L25/18 , H01L23/48 , H01L25/00 , H01L23/00 , H01L23/538 , H01L23/522 , H01L25/16 , H01L25/065
Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
-
6.
公开(公告)号:US20180226381A1
公开(公告)日:2018-08-09
申请号:US15863821
申请日:2018-01-05
Applicant: Intel Corporation
Inventor: KYU-OH LEE , ISLAM A. SALAMA , RAM S. VISWANATH , ROBERT L. SANKMAN , BABAK SABI , SRI CHAITRA JYOTSNA CHAVALI
IPC: H01L25/065 , H01L23/00 , H01L23/498
Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.
-
公开(公告)号:US20170168235A1
公开(公告)日:2017-06-15
申请号:US14964426
申请日:2015-12-09
Applicant: Intel Corporation
Inventor: ZHICHAO ZHANG , KEMAL AYGUN , ROBERT L. SANKMAN
CPC classification number: G02B6/12004 , G02B6/4257 , G02B6/428 , G02B6/4295 , G02B2006/12121 , G02B2006/12142 , G02B2006/12147
Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.
-
公开(公告)号:US20190103385A1
公开(公告)日:2019-04-04
申请号:US15721235
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: OMKAR KARHADE , ROBERT L. SANKMAN , NITIN A. DESHPANDE , MITUL MODI , THOMAS J. DE BONIS , ROBERT M. NICKERSON , ZHIMIN WAN , HAIFA HARIRI , SRI CHAITRA J. CHAVALI , NAZMIYE ACIKGOZ AKBAY , FADI Y. HAFEZ , CHRISTOPHER L. RUMER
IPC: H01L25/10 , H01L23/367 , H01L23/373 , H01L25/00
Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.
-
9.
公开(公告)号:US20170207196A1
公开(公告)日:2017-07-20
申请号:US15038008
申请日:2015-06-25
Applicant: Intel Corporation
Inventor: KYU-OH LEE , ISLAM A. SALAMA , RAM S. VISWANATH , ROBERT L. SANKMAN , BABAK SABI , SRI CHAITRA JYOTSNA CHAVALI
IPC: H01L25/065 , H01L23/498 , H01L23/00
CPC classification number: H01L25/0657 , H01L23/13 , H01L23/48 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/05 , H01L24/11 , H01L24/17 , H01L25/105 , H01L2224/0401 , H01L2224/05147 , H01L2224/16225 , H01L2224/97 , H01L2225/06517 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/15311
Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed
-
-
-
-
-
-
-
-