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    IN-PACKAGE 3D ANTENNA
    2.
    发明申请
    IN-PACKAGE 3D ANTENNA 审中-公开

    公开(公告)号：US20200243956A1

    公开(公告)日：2020-07-30

    申请号：US16258573

    申请日：2019-01-26

    Applicant: INTEL CORPORATION

    Inventor： ZHENGUO JIANG ,  OMKAR KARHADE ,  SRICHAITRA CHAVALI ,  ZHICHAO ZHANG ,  JIMIN YAO ,  STEPHEN SMITH ,  XIAOQIAN LI ,  ROBERT L. SANKMAN

    IPC: H01Q1/38 ,  H01L23/00 ,  H01Q1/22 ,  H01L21/56

    Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.

    CHIP-TO-CHIP INTERCONNECT WITH EMBEDDED ELECTRO-OPTICAL BRIDGE STRUCTURES
    3.
    发明申请
    CHIP-TO-CHIP INTERCONNECT WITH EMBEDDED ELECTRO-OPTICAL BRIDGE STRUCTURES 审中-公开

    公开(公告)号：US20180372952A1

    公开(公告)日：2018-12-27

    申请号：US15979382

    申请日：2018-05-14

    Applicant: Intel Corporation

    Inventor： ZHICHAO ZHANG ,  KEMAL AYGUN ,  ROBERT L. SANKMAN

    IPC: G02B6/12 ,  G02B6/42

    CPC classification number: G02B6/12004 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4295 ,  G02B6/43 ,  G02B2006/12121 ,  G02B2006/12142 ,  G02B2006/12147

    Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.

    DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE
    5.
    发明申请
    DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE 审中-公开

    公开(公告)号：US20200312833A1

    公开(公告)日：2020-10-01

    申请号：US16902123

    申请日：2020-06-15

    Applicant: INTEL CORPORATION

    Inventor： WILFRED GOMES ,  MARK T. BOHR ,  RAJESH KUMAR ,  ROBERT L. SANKMAN ,  RAVINDRANATH V. MAHAJAN ,  WESLEY D. MC CULLOUGH

    IPC: H01L25/18 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522 ,  H01L25/16 ,  H01L25/065

    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

    CHIP-TO-CHIP INTERCONNECT WITH EMBEDDED ELECTRO-OPTICAL BRIDGE STRUCTURES
    7.
    发明申请
    CHIP-TO-CHIP INTERCONNECT WITH EMBEDDED ELECTRO-OPTICAL BRIDGE STRUCTURES 有权

    公开(公告)号：US20170168235A1

    公开(公告)日：2017-06-15

    申请号：US14964426

    申请日：2015-12-09

    Applicant: Intel Corporation

    Inventor： ZHICHAO ZHANG ,  KEMAL AYGUN ,  ROBERT L. SANKMAN

    IPC: G02B6/12 ,  G02B6/42

    CPC classification number: G02B6/12004 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4295 ,  G02B2006/12121 ,  G02B2006/12142 ,  G02B2006/12147

    Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.

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