公开(公告)号：US20240354190A1

公开(公告)日：2024-10-24

申请号：US18759122

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Junjing SHI ,  Wei YANG ,  Amir Ali RADJAI ,  Hongjiu LU

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1004

Abstract: Examples include techniques associated with use of a memory tag with in-line or in-band error correction code (IBECC) memory to provide protection for data to be stored in an address space of a memory device. Examples include adding or including the memory tag with a single error correction double error detection (SECDED) code based on the data to provide IBECC for the data when stored to the first address space in the memory device.

公开(公告)号：US20200257566A1

公开(公告)日：2020-08-13

申请号：US16642523

申请日：2018-08-30

Applicant: INTEL CORPORATION

Inventor： Mrittika GANGULI ,  Ananth S. NARAYAN ,  Malini K. BHANDARU ,  Mohan J. KUMAR ,  Wei YANG ,  Lin YANG ,  Nathaniel POTTER ,  Madhuri KUMARI

IPC: G06F9/50 ,  G06F9/44 ,  G06F1/18 ,  G06F1/20 ,  G06F15/78 ,  G06F13/40 ,  H05K7/14 ,  H05K7/20

Abstract: Technologies for managing disaggregated resources in a data center includes a compute device configured to determine that a service related task has been generated and create one or more microservices to perform the created service related task using at least one of a plurality of services managed by the microservice resource controller circuitry. The compute device is further configuration to generate one or more microtasks to compose at least one service based on the one or more microservices. Other embodiments are described herein.