公开(公告)号：US20240354190A1

公开(公告)日：2024-10-24

申请号：US18759122

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Junjing SHI ,  Wei YANG ,  Amir Ali RADJAI ,  Hongjiu LU

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1004

Abstract: Examples include techniques associated with use of a memory tag with in-line or in-band error correction code (IBECC) memory to provide protection for data to be stored in an address space of a memory device. Examples include adding or including the memory tag with a single error correction double error detection (SECDED) code based on the data to provide IBECC for the data when stored to the first address space in the memory device.

公开(公告)号：US20250028532A1

公开(公告)日：2025-01-23

申请号：US18375488

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Jason AGRON ,  Andreas KLEEN ,  Ching-Tsun CHOU ,  Jonathan COMBS ,  Hongjiu LU ,  Jared Warner STARK, IV ,  Jeff WIEDEMEIER

IPC: G06F9/30

Abstract: Techniques for performing an unconditional jump are described. In some examples, an instruction is processed to perform the unconditional jump. In some examples, the instruction is to at least include one or more fields for an opcode and a 64-bit bit immediate, wherein the 64-bit immediate is to encode an absolute address and the opcode is to indicate execution circuitry is jump to the absolute address.