公开(公告)号：US20190102097A1

公开(公告)日：2019-04-04

申请号：US15721351

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Naveen Vittal Prabhu ,  Yu Du ,  Purval Shyam Sule

IPC: G06F3/06

Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

公开(公告)号：US10585791B2

公开(公告)日：2020-03-10

申请号：US15925907

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Yu Du ,  Ryan Norton ,  David J. Pelster ,  Xin Guo

IPC: G06F12/02 ,  G06F7/58 ,  G06F12/06

Abstract: An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.

公开(公告)号：US10521121B2

公开(公告)日：2019-12-31

申请号：US15394653

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： David B. Carlton ,  Xin Guo ,  Yu Du

IPC: G06F12/02 ,  G06F3/06

Abstract: Provided are an apparatus, system and method for apparatus, system and method for throttling an acceptance rate for adding host Input/Output (I/O) commands to a buffer in a non-volatile memory storage device. Information is maintained on an input rate at which I/O commands are being added to the buffer and information is maintained on an output rate at which I/O commands are processed from the buffer to apply to execute against the non-volatile memory. A determination is made of a current level of available space in the buffer and an acceptance rate at which I/O commands are added to the buffer from the host system to process based on the input rate, the output rate, the current level of available space, and an available space threshold for the buffer to maintain the buffer at the available space threshold. I/O commands are added to the buffer to process based on the acceptance rate. The I/O commands are accessed from the buffer to process to execute against the non-volatile memory.

公开(公告)号：US10453540B2

公开(公告)日：2019-10-22

申请号：US15959538

申请日：2018-04-23

Applicant: Intel Corporation

Inventor： Xin Guo ,  Yu Du ,  Curtis Gittens ,  David J. Pelster ,  Donia Sebastian

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G06F3/06 ,  G06F13/18

Abstract: A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.

公开(公告)号：US10268407B1

公开(公告)日：2019-04-23

申请号：US15721351

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Naveen Vittal Prabhu ,  Yu Du ,  Purval Shyam Sule

IPC: G11C16/26 ,  G06F3/06

Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

公开(公告)号：US20190042403A1

公开(公告)日：2019-02-07

申请号：US15925907

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Yu Du ,  Ryan Norton ,  David J. Pelster ,  Xin Guo

IPC: G06F12/02 ,  G06F7/58

CPC classification number: G06F12/0223 ,  G06F7/58 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/0607 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/7208

Abstract: An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.

公开(公告)号：US10372446B2

公开(公告)日：2019-08-06

申请号：US15640484

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： David J. Pelster ,  Sudhakar Ayyasamy ,  Mark Anthony S. Golez ,  Yogesh B. Wakchaure ,  Yu Du

IPC: G06F13/00 ,  G06F9/30 ,  G06F12/02 ,  G06F15/78 ,  H03K19/177 ,  G06F3/06 ,  G06F12/06 ,  G06F11/00

Abstract: Technology to dynamically modulate read granularity of a memory device. A computing system may include a controller and one or more memory devices coupled to the controller, the one or more memory devices including instructions, which when executed by the controller, may cause the computing system to determine whether a read to a memory device satisfies a sub-page read policy. In addition, the instructions, when executed, may cause the computing system to issue a sub-page read command to retrieve data from the memory device at sub-page granularity when the read satisfies the sub-page read policy. Moreover, the instructions, when executed, may cause the computing system to issue a full-page read command to retrieve the data at full-page granularity when the read does not satisfy the sub-page read policy or when a read for a segment of sequentially stored data does not satisfy the sub-page read policy.

公开(公告)号：US20190004796A1

公开(公告)日：2019-01-03

申请号：US15640484

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： David J. Pelster ,  Sudhakar Ayyasamy ,  Mark Anthony S. Golez ,  Yogesh B. Wakchaure ,  Yu Du

IPC: G06F9/30 ,  G06F12/02 ,  G06F15/78 ,  H03K19/177 ,  G06F3/06 ,  G06F12/06 ,  G06F11/00

CPC classification number: G06F9/30003 ,  G06F3/0611 ,  G06F11/004 ,  G06F12/0238 ,  G06F12/0638 ,  G06F15/7867 ,  H03K19/1776

Abstract: Technology to dynamically modulate read granularity of a memory device. A computing system may include a controller and one or more memory devices coupled to the controller, the one or more memory devices including instructions, which when executed by the controller, may cause the computing system to determine whether a read to a memory device satisfies a sub-page read policy. In addition, the instructions, when executed, may cause the computing system to issue a sub-page read command to retrieve data from the memory device at sub-page granularity when the read satisfies the sub-page read policy. Moreover, the instructions, when executed, may cause the computing system to issue a full-page read command to retrieve the data at full-page granularity when the read does not satisfy the sub-page read policy or when a read for a segment of sequentially stored data does not satisfy the sub-page read policy.