公开(公告)号：US20200300912A1

公开(公告)日：2020-09-24

申请号：US16361816

申请日：2019-03-22

Applicant: INTEL CORPORATION

Inventor： Jesse ARMAGOST ,  Nathan BLACKWELL ,  Matthew BOELTER ,  Geoffrey KELLY ,  James NEEB ,  Sundar PATHY ,  Yu ZHANG ,  Shelby ROLLINS

IPC: G01R31/317 ,  G01R31/319

Abstract: Embodiments described herein may be directed to receiving a plurality of data captured, respectively, by a plurality of test instruments coupled to a device under test, wherein a plurality of data elements within, respectively, the plurality of captured data are associated with a timestamp based upon a time a data element was captured. Embodiments may also analyze the received plurality of data captured, respectively, by the one or more test instruments, and graphically display at least a portion of the analyzed plurality of captured data to a user. Other embodiments may be identified herein.

公开(公告)号：US20220130742A1

公开(公告)日：2022-04-28

申请号：US17566523

申请日：2021-12-30

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC: H01L23/498

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20240105572A1

公开(公告)日：2024-03-28

申请号：US18530006

申请日：2023-12-05

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/486 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20230014579A1

公开(公告)日：2023-01-19

申请号：US17956766

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC: H01L23/498

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20190333848A1

公开(公告)日：2019-10-31

申请号：US16509387

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC: H01L23/498

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.