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    PACKAGE SUBSTRATES WITH MAGNETIC BUILD-UP LAYERS
    2.
    发明申请
    PACKAGE SUBSTRATES WITH MAGNETIC BUILD-UP LAYERS 有权

    公开(公告)号：US20210327795A1

    公开(公告)日：2021-10-21

    申请号：US17360701

    申请日：2021-06-28

    申请人： Intel Corporation

    发明人： Zhiguo QIAN ,  Kaladhar RADHAKRISHNAN ,  Kemal AYGUN

    IPC分类号： H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00

    摘要： The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

    GROUND PLANE VERTICAL ISOLATION OF, GROUND LINE COAXIAL ISOLATION OF, AND IMPEDANCE TUNING OF HORIZONTAL DATA SIGNAL TRANSMISSION LINES ROUTED THROUGH PACKAGE DEVICES
    3.
    发明申请
    GROUND PLANE VERTICAL ISOLATION OF, GROUND LINE COAXIAL ISOLATION OF, AND IMPEDANCE TUNING OF HORIZONTAL DATA SIGNAL TRANSMISSION LINES ROUTED THROUGH PACKAGE DEVICES 审中-公开

    公开(公告)号：US20180374804A1

    公开(公告)日：2018-12-27

    申请号：US15774958

    申请日：2015-12-26

    申请人： Intel Corporation

    发明人： Yu Amos ZHANG ,  Gabriel S. REGALADO ,  Zhiguo QIAN ,  Kemal AYGUN

    IPC分类号： H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01P3/06 ,  H01P11/00

    摘要： A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.

    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION
    5.
    发明公开
    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 审中-公开

    公开(公告)号：US20240105572A1

    公开(公告)日：2024-03-28

    申请号：US18530006

    申请日：2023-12-05

    申请人： Intel Corporation

    发明人： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

    IPC分类号： H01L23/498

    CPC分类号： H01L23/49827 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/486 ,  H01L2924/0002

    摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION
    6.
    发明申请
    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 有权

    公开(公告)号：US20230014579A1

    公开(公告)日：2023-01-19

    申请号：US17956766

    申请日：2022-09-29

    申请人： Intel Corporation

    发明人： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

    IPC分类号： H01L23/498

    摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION
    7.
    发明申请
    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 审中-公开

    公开(公告)号：US20190333848A1

    公开(公告)日：2019-10-31

    申请号：US16509387

    申请日：2019-07-11

    申请人： Intel Corporation

    发明人： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

    IPC分类号： H01L23/498

    摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.