公开(公告)号：US20230090188A1

公开(公告)日：2023-03-23

申请号：US17481001

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Junxin WANG ,  Kemal AYGUN ,  Jieying KONG ,  Ala OMER ,  Whitney M. BRYKS

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538

Abstract: An apparatus is described. The apparatus includes a semiconductor chip package substrate having alternating metal and dielectric layers. First and second ones of the dielectric layers that are directly above and directly below a first of the metal layers that is patterned to have supply and/or reference voltage structures have respectively higher dielectric constant (Dk) and higher dissipation factor (Df) than third and fourth ones of the dielectric layers that are directly above and directly below a second of the metal layers that is patterned to have signal wires that are to transport signals having a pulse width of 1 ns or less.

公开(公告)号：US20210327795A1

公开(公告)日：2021-10-21

申请号：US17360701

申请日：2021-06-28

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kaladhar RADHAKRISHNAN ,  Kemal AYGUN

IPC: H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20180374804A1

公开(公告)日：2018-12-27

申请号：US15774958

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Gabriel S. REGALADO ,  Zhiguo QIAN ,  Kemal AYGUN

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01P3/06 ,  H01P11/00

Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.

公开(公告)号：US20180331043A1

公开(公告)日：2018-11-15

申请号：US15774257

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Zhiguo QIAN ,  Kemal AYGUN ,  Yidnekachew S. MEKONNEN ,  Gregorio R. MURTAGIAN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Jeff C. MORRISS

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/552

CPC classification number: H01L23/5384 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L24/00 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.

公开(公告)号：US20240105572A1

公开(公告)日：2024-03-28

申请号：US18530006

申请日：2023-12-05

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/486 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20230014579A1

公开(公告)日：2023-01-19

申请号：US17956766

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC: H01L23/498

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20190333848A1

公开(公告)日：2019-10-31

申请号：US16509387

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC: H01L23/498

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20190311963A1

公开(公告)日：2019-10-10

申请号：US15945641

申请日：2018-04-04

Applicant: Intel Corporation

Inventor： Stephen CHRISTIANSON ,  Stephen HALL ,  Emile DAVIES-VENN ,  Dong-Ho HAN ,  Kemal AYGUN ,  Konika GANGULY ,  Jun LIAO ,  M. Reza ZAMANI ,  Cory MASON ,  Kirankumar KAMISETTY

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01P3/08 ,  H01P11/00 ,  H01L21/48

Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.

公开(公告)号：US20180005965A1

公开(公告)日：2018-01-04

申请号：US15201375

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Jihwan KIM ,  Ajay BALANKUTTY ,  Anupriya SRIRAMULU ,  MD. Mohiuddin MAZUMDER ,  Frank O'MAHONY ,  Zuoguo WU ,  Kemal AYGUN

IPC: H01L23/64 ,  H01L23/66 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/645 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0288 ,  H02H9/046

Abstract: Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.

公开(公告)号：US20240070366A1

公开(公告)日：2024-02-29

申请号：US17895107

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Nicholas HAEHN ,  Raquel DE SOUZA BORGES FERREIRA ,  Siddharth ALUR ,  Prakaram JOSHI ,  Dhanya ATHREYA ,  Yidnekachew MEKONNEN ,  Ali HARIRI ,  Andrea NICOLAS ,  Sri Chaitra Jyotsna CHAVALI ,  Kemal AYGUN

IPC: G06F30/392 ,  H01L23/498

CPC classification number: G06F30/392 ,  H01L23/49838 ,  G06F2119/22 ,  H01L23/49822

Abstract: A package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.