公开(公告)号：US20180011813A1

公开(公告)日：2018-01-11

申请号：US15202910

申请日：2016-07-06

Applicant: INTEL IP CORPORATION

Inventor： Eytan Mann ,  Gilad Nahor ,  Guy Kaminitz

IPC: G06F13/42 ,  G06F1/10 ,  G06F1/32 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F1/10 ,  G06F1/3287 ,  G06F13/4022

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for a serial mid-speed interface. A first component includes a phase-locked loop (PLL) to receive an input clock signal and to output an output signal, an interface controller including a clock-management state machine, and a transmitter. The interface controller is to receive the input clock signal, receive the output signal from the PLL, and generate a speed-switch packet. The transmitter is to transmit a first plurality of packets to a second component at a clock rate based on the clock signal via a mid-speed interface, transmit the speed-switch packet to the second component, and transmit a second plurality of packets to the second component at a PLL rate based on the output signal, where the PLL rate is greater than the clock rate.