公开(公告)号：US20190253058A1

公开(公告)日：2019-08-15

申请号：US16329312

申请日：2016-09-29

申请人： INTEL IP CORPORATION

发明人： Ashoke Ravi ,  Rotem Banin ,  Ofir Degani ,  David Ben-Haim ,  Yigal Kalmanovich

IPC分类号： H03L7/099 ,  H03L7/093 ,  H04L7/08 ,  H04L7/033

CPC分类号： H03L7/0995 ,  H03L7/093 ,  H03L2207/50 ,  H04L7/0331 ,  H04L7/08

摘要： For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.