公开(公告)号：US20160131706A1

公开(公告)日：2016-05-12

申请号：US14995353

申请日：2016-01-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  John R. GOSS ,  Eric D. HUNT-SCHROEDER ,  Andrew K. KILLORIN

IPC: G01R31/3177

CPC classification number: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure

Abstract translation: 提供了系统和方法，用于在扫描链中实现客户透明的逻辑冗余，以提高集成电路的产量。 更具体地，提供了包括多个组合的锁存结构的集成电路结构。 组合的锁存结构中的每一个包括原始锁存器和冗余锁存器。 集成电路结构还包括多个组合的逻辑结构。 组合逻辑结构中的每一个包括原始逻辑结构冗余逻辑结构。 每个冗余锁存器是组合锁存结构内的每个相应原始锁存器的副本，并且每个冗余逻辑结构是组合逻辑结构内的每个相应的原始逻辑结构的副本，使得锁存器和逻辑的两倍库被提供给一个 或更多的集成电路结构的扫描链

公开(公告)号：US20210116498A1

公开(公告)日：2021-04-22

申请号：US17132820

申请日：2020-12-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  John R. GOSS ,  Eric D. HUNT-SCHROEDER ,  Andrew K. KILLORIN

IPC: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

公开(公告)号：US20200072902A1

公开(公告)日：2020-03-05

申请号：US16676776

申请日：2019-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  John R. GOSS ,  Eric D. HUNT-SCHROEDER ,  Andrew K. KILLORIN

IPC: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

公开(公告)号：US20170370990A1

公开(公告)日：2017-12-28

申请号：US15700597

申请日：2017-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  John R. GOSS ,  Eric D. HUNT-SCHROEDER ,  Andrew K. KILLORIN

IPC: G01R31/3177

CPC classification number: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.