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公开(公告)号：US20160131706A1
公开(公告)日：2016-05-12
申请号：US14995353
申请日：2016-01-14
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177
摘要： Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure
摘要翻译： 提供了系统和方法，用于在扫描链中实现客户透明的逻辑冗余，以提高集成电路的产量。 更具体地，提供了包括多个组合的锁存结构的集成电路结构。 组合的锁存结构中的每一个包括原始锁存器和冗余锁存器。 集成电路结构还包括多个组合的逻辑结构。 组合逻辑结构中的每一个包括原始逻辑结构冗余逻辑结构。 每个冗余锁存器是组合锁存结构内的每个相应原始锁存器的副本，并且每个冗余逻辑结构是组合逻辑结构内的每个相应的原始逻辑结构的副本，使得锁存器和逻辑的两倍库被提供给一个 或更多的集成电路结构的扫描链
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公开(公告)号：US20210116498A1
公开(公告)日：2021-04-22
申请号：US17132820
申请日：2020-12-23
IPC分类号： G01R31/3177
摘要： Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
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3.发明申请公开(公告)号：US20200075119A1
公开(公告)日：2020-03-05
申请号：US16675783
申请日：2019-11-06
发明人： Aravindan J. BUSI , John R. GOSS , Paul J. GRZYMKOWSKI , Krishnendu MONDAL , Kiran K. NARAYAN , Michael R. OUELLETTE , Michael A. ZIEGERHOFER
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
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4.发明申请公开(公告)号：US20180053566A1
公开(公告)日：2018-02-22
申请号：US15798858
申请日：2017-10-31
发明人： Aravindan J. BUSI , John R. GOSS , Paul J. GRZYMKOWSKI , Krishnendu MONDAL , Kiran K. NARAYAN , Michael R. OUELLETTE , Michael A. ZIEGERHOFER
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
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公开(公告)号：US20170018313A1
公开(公告)日：2017-01-19
申请号：US14800067
申请日：2015-07-15
发明人： Aravindan J. BUSI , John R. GOSS , Paul J. GRZYMKOWSKI , Krishnendu MONDAL , Kiran K. NARAYAN , Michael R. OUELLETTE , Michael A. ZIEGERHOFER
CPC分类号： G11C29/38 , G11C29/40 , G11C29/44 , G11C29/4401 , G11C29/56004 , G11C29/70 , G11C2029/3602
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
摘要翻译： BIST引擎被配置为在存储器BIST运行期间存储每个基于模式的失败状态及其相关过程。 该方法包括在至少一个存储设备中测试多个模式，并且在每个模式的执行期间确定多个模式中的哪个模式已经检测到失败。 该方法还包括存储每个检测到的故障模式的每个基于模式的失败状态。
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公开(公告)号：US20200072902A1
公开(公告)日：2020-03-05
申请号：US16676776
申请日：2019-11-07
IPC分类号： G01R31/3177
摘要： Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
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7.发明申请公开(公告)号：US20180061509A1
公开(公告)日：2018-03-01
申请号：US15801444
申请日：2017-11-02
发明人： Aravindan J. BUSI , John R. GOSS , Paul J. GRZYMKOWSKI , Krishnendu MONDAL , Kiran K. NARAYAN , Michael R. OUELLETTE , Michael A. ZIEGERHOFER
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
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公开(公告)号：US20170370990A1
公开(公告)日：2017-12-28
申请号：US15700597
申请日：2017-09-11
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177
摘要： Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
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