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    CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD
    1.
    发明申请
    CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD 有权
    客户透明的逻辑冗余改善投资

    公开(公告)号：US20160131706A1

    公开(公告)日：2016-05-12

    申请号：US14995353

    申请日：2016-01-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Igor ARSOVSKI ,  John R. GOSS ,  Eric D. HUNT-SCHROEDER ,  Andrew K. KILLORIN

    IPC: G01R31/3177

    CPC classification number: G01R31/3177

    Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure

    Abstract translation: 提供了系统和方法，用于在扫描链中实现客户透明的逻辑冗余，以提高集成电路的产量。 更具体地，提供了包括多个组合的锁存结构的集成电路结构。 组合的锁存结构中的每一个包括原始锁存器和冗余锁存器。 集成电路结构还包括多个组合的逻辑结构。 组合逻辑结构中的每一个包括原始逻辑结构冗余逻辑结构。 每个冗余锁存器是组合锁存结构内的每个相应原始锁存器的副本，并且每个冗余逻辑结构是组合逻辑结构内的每个相应的原始逻辑结构的副本，使得锁存器和逻辑的两倍库被提供给一个 或更多的集成电路结构的扫描链

    LIMITING SKEW BETWEEN DIFFERENT DEVICE TYPES TO MEET PERFORMANCE REQUIREMENTS OF AN INTEGRATED CIRCUIT
    2.
    发明申请
    LIMITING SKEW BETWEEN DIFFERENT DEVICE TYPES TO MEET PERFORMANCE REQUIREMENTS OF AN INTEGRATED CIRCUIT 有权
    不同设备之间的限制条件符合集成电路的性能要求

    公开(公告)号：US20150242560A1

    公开(公告)日：2015-08-27

    申请号：US14190723

    申请日：2014-02-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Igor ARSOVSKI ,  Jeanne P. BICKFORD ,  Mark W. KUEMERLE

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

    Abstract: Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.

    Abstract translation: 提供的方法和系统被设计为施加n型到p型装置偏斜约束，该约束超出正常技术限制允许以在较低电压下操作半导体器件，同时仍然在较低功率下实现类似的性能。 更具体地，提供了一种方法，其包括：针对至少一个库元素设置设备偏斜要求，基于设置的设备偏差要求来设置用于至少一个库元素的设备偏斜测试配置，使用设备来设计至少一个库元素 在产品上制造包括至少一个设备偏斜监视器的至少一个库元件，使用至少一个设备偏斜监视器确定所制造的至少一个库元件的实际设备偏差，以及确定所制造的产品 达到目标规格。

    CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD
    3.
    发明申请
    CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD 有权

    公开(公告)号：US20210116498A1

    公开(公告)日：2021-04-22

    申请号：US17132820

    申请日：2020-12-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Igor ARSOVSKI ,  John R. GOSS ,  Eric D. HUNT-SCHROEDER ,  Andrew K. KILLORIN

    IPC: G01R31/3177

    Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

    CONVERTING AN XY TCAM TO A VALUE TCAM
    5.
    发明申请
    CONVERTING AN XY TCAM TO A VALUE TCAM 有权
    将XY TCAM转换为值TCAM

    公开(公告)号：US20150200011A1

    公开(公告)日：2015-07-16

    申请号：US14152345

    申请日：2014-01-10

    Applicant: International Business Machines Corporation

    Inventor： Igor ARSOVSKI

    IPC: G11C15/04

    CPC classification number: G11C15/046 ,  G06F11/1064 ,  G06F17/30982 ,  G11C11/417 ,  G11C15/04 ,  H04L45/7457

    Abstract: Approaches for an integrated circuit ternary content addressable memory (TCAM) are provided. A system includes an array of XY TCAM cells and respective translation circuits connected to respective pairs of the XY TCAM cells. The system also includes a memory controller structured to provide control signals to the respective translation circuits. The memory controller and respective translation circuits are structured to control the array of XY TCAM cells to perform single cycle update and single cycle search operations.

    Abstract translation: 提供了集成电路三元内容可寻址存储器（TCAM）的方法。 一种系统包括XY TCAM单元的阵列和连接到相应的XY TCAM单元对的各自的平移电路。 该系统还包括构造成向相应的转换电路提供控制信号的存储器控​​制器。 存储器控制器和各自的平移电路被构造为控制XY TCAM单元的阵列以执行单周期更新和单周期搜索操作。

    CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD
    7.
    发明申请
    CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD 审中-公开

    公开(公告)号：US20200072902A1

    公开(公告)日：2020-03-05

    申请号：US16676776

    申请日：2019-11-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Igor ARSOVSKI ,  John R. GOSS ,  Eric D. HUNT-SCHROEDER ,  Andrew K. KILLORIN

    IPC: G01R31/3177

    Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

    CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD
    8.
    发明申请
    CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD 审中-公开

    公开(公告)号：US20170370990A1

    公开(公告)日：2017-12-28

    申请号：US15700597

    申请日：2017-09-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Igor ARSOVSKI ,  John R. GOSS ,  Eric D. HUNT-SCHROEDER ,  Andrew K. KILLORIN

    IPC: G01R31/3177

    CPC classification number: G01R31/3177

    Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

    COMPOSITE VIEWS FOR IP BLOCKS IN ASIC DESIGNS
    10.
    发明申请
    COMPOSITE VIEWS FOR IP BLOCKS IN ASIC DESIGNS 有权
    用于ASIC设计中的IP块的复合视图

    公开(公告)号：US20160364516A1

    公开(公告)日：2016-12-15

    申请号：US14734411

    申请日：2015-06-09

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Igor ARSOVSKI ,  Mark W. KUEMERLE ,  Qing LI

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5027 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5077 ,  G06F2217/06 ,  G06F2217/66 ,  G06F2217/84

    Abstract: A computing device for a generating composite view for an intellectual property (IP) core may obtain constraints for multiple application specific integrated circuits (ASIC) designs in which the IP core is used; and determine composite constraints for the IP core based on the constraints for the multiple ASIC designs. The composite constraints may be within all constraints for the multiple ASIC designs. A freedom of change to update the particular IP core may be identified based on the composite constraints.

    Abstract translation: 用于知识产权（IP）核心的生成复合视图的计算设备可以获得其中使用IP核的多个专用集成电路（ASIC）设计的约束; 并基于多个ASIC设计的约束来确定IP核的复合约束。 复合约束可以在多个ASIC设计的所有约束内。 可以基于复合约束来识别更新特定IP核的自由。

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