公开(公告)号：US11966776B2

公开(公告)日：2024-04-23

申请号：US17305784

申请日：2021-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Aporva Amarnath ,  Augusto Vega ,  Alper Buyuktosunoglu ,  Hubertus Franke ,  John-David Wellman ,  Pradip Bose

IPC: G06F9/46 ,  G06F9/445 ,  G06F9/48 ,  G06N20/00

CPC classification number: G06F9/4881 ,  G06F9/44505 ,  G06F9/485 ,  G06N20/00

Abstract: Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

公开(公告)号：US20250054156A1

公开(公告)日：2025-02-13

申请号：US18230830

申请日：2023-08-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sharon Ladron de Guevara Contreras ,  Augusto Vega ,  Aporva Amarnath ,  Pradip Bose

IPC: G06T7/11 ,  G01S17/89 ,  G06T7/50 ,  G06T7/62 ,  G06V10/25 ,  G06V10/764

Abstract: A method, computer program product, and computer system for segmenting camera images obtained by a digital camera and analyzing the segments by a machine learning model (MLM). A first and second digital image of a scene obtained by a digital camera and a depth sensor, respectively, are received. The first and second digital images are characterized by a first and second pixel configuration, respectively. Using the second digital image, a binary mask characterized by the second pixel configuration is generated, including selectively digitizing each pixel of the binary mask to 1 or 0 to identify one or more regions of the scene to be subsequently segmented from the first digital image. By applying the binary mask to the first digital image, segments of the first digital image are generated. Each generated segment corresponds to a subset of the pixels of the binary mask that are digitized to 1.

公开(公告)号：US11740933B2

公开(公告)日：2023-08-29

申请号：US16917981

申请日：2020-07-01

Applicant: International Business Machines Corporation

Inventor： Augusto Vega ,  Alper Buyuktosunoglu ,  Hubertus Franke ,  John-David Wellman ,  Pradip Bose ,  Robert Matthew Senger ,  Aporva Amarnath

IPC: G06F9/46 ,  G06F9/48 ,  G06F16/901 ,  G06N20/00 ,  G06N5/043

CPC classification number: G06F9/4881 ,  G06F16/9024 ,  G06N5/043 ,  G06N20/00

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.

公开(公告)号：US11704155B2

公开(公告)日：2023-07-18

申请号：US16917975

申请日：2020-07-01

Applicant: International Business Machines Corporation

Inventor： Augusto Vega ,  Alper Buyuktosunoglu ,  Hubertus Franke ,  John-David Wellman ,  Pradip Bose ,  Robert Matthew Senger ,  Aporva Amarnath

IPC: G06F9/48 ,  G06Q20/14 ,  G06F16/901

CPC classification number: G06F9/4893 ,  G06F16/9024 ,  G06Q20/145 ,  G06F2209/486

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

公开(公告)号：US20220004433A1

公开(公告)日：2022-01-06

申请号：US16917975

申请日：2020-07-01

Applicant: International Business Machines Corporation

Inventor： Augusto Vega ,  Alper Buyuktosunoglu ,  Hubertus Franke ,  John-David Wellman ,  Pradip Bose ,  Robert Matthew Senger ,  Aporva Amarnath

IPC: G06F9/48 ,  G06F16/901 ,  G06Q20/14

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

公开(公告)号：US20220004430A1

公开(公告)日：2022-01-06

申请号：US16917981

申请日：2020-07-01

Applicant: International Business Machines Corporation

Inventor： Augusto Vega ,  Alper Buyuktosunoglu ,  Hubertus Franke ,  John-David Wellman ,  Pradip Bose ,  Robert Matthew Senger ,  Aporva Amarnath

IPC: G06F9/48 ,  G06N5/04 ,  G06N20/00 ,  G06F16/901

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.