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公开(公告)号：US11687337B2
公开(公告)日：2023-06-27
申请号：US17445541
申请日：2021-08-20
发明人： Bryan Lloyd , Brian Chen , Kimberly M. Fernsler
CPC分类号： G06F9/30043 , G06F9/3836
摘要： A method for operation of a processor core is provided. A rejected first load instruction is received that has been rejected due to a false load-hit-store detection against a first store instruction. A warning label is generated on a basis of the false load-hit-store detection. The warning label is added to the received first load instruction to create a labeled first load instruction. The labeled first load instruction is issued such that the warning label causes the labeled first load instruction to bypass the first store instruction in the store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.
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公开(公告)号：US20220035748A1
公开(公告)日：2022-02-03
申请号：US16941630
申请日：2020-07-29
发明人： David Campbell , Bryan Lloyd , David A. Hrusecky , Kimberly M. Fernsler , Jeffrey A. Stuecheli , Guy L. Guthrie , SAMUEL DAVID KIRCHHOFF , Robert A. Cordes , Michael J. Mack , Brian Chen
IPC分类号： G06F12/1045 , G06F12/0891 , G06F9/30 , G06F9/54
摘要： Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.
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公开(公告)号：US20220019436A1
公开(公告)日：2022-01-20
申请号：US16933241
申请日：2020-07-20
发明人： Bryan Lloyd , Sundeep Chadha , Dung Q. Nguyen , Christian Gerhard Zoellin , Brian W. Thompto , Sheldon Bernard Levenstein , Phillip G. Williams , Robert A. Cordes , Brian Chen
摘要： Provided is a method for fusing store instructions in a microprocessor. The method includes identifying two instructions in an execution pipeline of a microprocessor. The method further includes determining that the two instructions meet a fusion criteria. In response to determining that the two instructions meet the fusion criteria, the two instructions are recoded into a fused instruction. The fused instruction is executed.
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公开(公告)号：US11314510B2
公开(公告)日：2022-04-26
申请号：US16994070
申请日：2020-08-14
IPC分类号： G06F9/30 , G06F12/0895 , G06F9/38 , G06F12/0817 , G06F12/0875
摘要： A computer system, processor, and/or load-store unit has a data cache for storing data, the data cache having a plurality of entries to store the data, each data cache entry addressed by a row and a Way, each data cache row having a plurality of the data cache Ways; a first Address Directory organized and arranged the same as the data cache where each first Address Directory entry is addressed by a row and a Way where each row has a plurality of Ways; a store reorder queue for tracking the store instructions; and a load reorder queue for tracking load instruction. Each of the load and store reorder queues having a Way bit field, preferably less than six bits, for identifying the data cache Way and/or a first Address Directory Way where the Way bit field acts as a proxy for a larger address, e.g. a real page number.
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公开(公告)号：US11321088B2
公开(公告)日：2022-05-03
申请号：US17002378
申请日：2020-08-25
IPC分类号： G06F9/30 , G06F12/0895 , G06F9/38 , G06F12/0817 , G06F12/0875
摘要： A computer system, processor, and/or load-store unit has a data cache for storing data, the data cache having a plurality of entries to store the data, each data cache entry addressed by a row and a Way, each data cache row having a plurality of the data cache Ways; a first Address Directory organized and arranged the same as the data cache where each first Address Directory entry is addressed by a row and a Way where each row has a plurality of Ways; a store reorder queue for tracking the store instructions; and a load reorder queue for tracking load instruction. Each of the load and store reorder queues having a Way bit field, preferably less than six bits, for identifying the data cache Way and/or a first Address Directory Way where the Way bit field acts as a proxy for a larger address, e.g. a real page number.
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6.发明授权公开(公告)号：US11243773B1
公开(公告)日：2022-02-08
申请号：US17120371
申请日：2020-12-14
发明人： Bryan Lloyd , David Campbell , Brian Chen , Robert A. Cordes
IPC分类号： G06F9/38
摘要： A computer system, includes a store queue that holds store entries and a load queue that holds load entries sleeping on a store entry. A processor detects a store drain merge operation call and generates a pair of store tags comprising a first store tag corresponding to a first store entry to be drained and a second store tag corresponding to a second store entry to be drained. The processor determines the pair of store tags an even-type store tag or an odd-type store tag. The processor disables the odd store tag included in the even-type store tag pair when detecting the even-type store tag pair, and wakes up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the even-type store tag pair while the odd store tag is disabled.
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公开(公告)号：US11379241B2
公开(公告)日：2022-07-05
申请号：US16943408
申请日：2020-07-30
摘要： System includes at least one computer processor having a load store execution unit (LSU) for processing load and store instructions, wherein the LSU includes (a) a store queue having a plurality of entries for storing data, each store queue entry having a data field for storing the data, the data field having a width for storing the data; and (b) a gather buffer for holding data, wherein the processor is configured to: process oversize data larger than the width of the data field of the store queue, and process an oversize load instruction for oversize data by executing two passes through the LSU, a first pass through the LSU configured to store a first portion of the oversize data in the gather buffer and a second pass through the LSU configured to merge the first portion of the oversize data with a second portion of the oversize data.
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公开(公告)号：US20220035631A1
公开(公告)日：2022-02-03
申请号：US16943408
申请日：2020-07-30
IPC分类号： G06F9/30
摘要： System includes at least one computer processor having a load store execution unit (LSU) for processing load and store instructions, wherein the LSU includes (a) a store queue having a plurality of entries for storing data, each store queue entry having a data field for storing the data, the data field having a width for storing the data; and (b) a gather buffer for holding data, wherein the processor is configured to: process oversize data larger than the width of the data field of the store queue, and process an oversize load instruction for oversize data by executing two passes through the LSU, a first pass through the LSU configured to store a first portion of the oversize data in the gather buffer and a second pass through the LSU configured to merge the first portion of the oversize data with a second portion of the oversize data.
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公开(公告)号：US20230056077A1
公开(公告)日：2023-02-23
申请号：US17445541
申请日：2021-08-20
发明人： Bryan Lloyd , Brian Chen , Kimberly M. Fernsler
摘要： A method for operation of a processor core is provided. A rejected first load instruction is received that has been rejected due to a false load-hit-store detection against a first store instruction. A warning label is generated on a basis of the false load-hit-store detection. The warning label is added to the received first load instruction to create a labeled first load instruction. The labeled first load instruction is issued such that the warning label causes the labeled first load instruction to bypass the first store instruction in the store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.
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公开(公告)号：US11263151B2
公开(公告)日：2022-03-01
申请号：US16941630
申请日：2020-07-29
发明人： David Campbell , Bryan Lloyd , David A. Hrusecky , Kimberly M. Fernsler , Jeffrey A. Stuecheli , Guy L. Guthrie , Samuel David Kirchhoff , Robert A. Cordes , Michael J. Mack , Brian Chen
IPC分类号： G06F12/00 , G06F12/1045 , G06F12/0891 , G06F9/54 , G06F9/30
摘要： Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.
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