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公开(公告)号：US11650926B2
公开(公告)日：2023-05-16
申请号：US17370229
申请日：2021-07-08
发明人： David Campbell , Bryan Lloyd
IPC分类号： G06F12/0877
CPC分类号： G06F12/0877 , G06F2212/151 , G06F2212/657
摘要： A system and method of handling data access demands in a processor virtual cache that includes: determining if a virtual cache data access demand missed because of a difference in the context tag of the data access demand and a corresponding entry in the virtual cache with the same virtual address as the data access demand; in response to the virtual cache missing, determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table.
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公开(公告)号：US11636043B2
公开(公告)日：2023-04-25
申请号：US17461919
申请日：2021-08-30
发明人： Charles D. Wait , Jake Truelove , David Campbell , Jody Joyner , Jon K. Kriegel , Glenn O. Kincaid
IPC分类号： G06F12/1009
摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.
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公开(公告)号：US20230062909A1
公开(公告)日：2023-03-02
申请号：US17461919
申请日：2021-08-30
发明人： Charles D. Wait , Jake Truelove , David Campbell , Jody Joyner , Jon K. Kriegel , Glenn O. Kincaid
IPC分类号： G06F12/1009
摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.
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公开(公告)号：US11461474B2
公开(公告)日：2022-10-04
申请号：US16751234
申请日：2020-01-24
发明人： Jentje Leenstra , Paul Mackerras , Benjamin Herrenschmidt , Bradly George Frey , John Martin Ludden , Guerney D. H. Hunt , David Campbell
摘要： The present disclosure relates to a process-based virtualization system comprising a data processing unit. The system comprises a computer readable storage media, wherein a first memory component of the computer readable storage media is configured for access by an OS, secure and non-secure applications and the firmware, and wherein a second memory component of the computer readable storage media is configured for access by the firmware and not by the OS and the non-secure application. The data processing unit is configured to operate in a first mode of operation that executes a non-secure application process using the OS, and to operate in a second mode of operation that executes the secure application using the firmware, thereby executing application code using the second memory component.
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公开(公告)号：US20220292028A1
公开(公告)日：2022-09-15
申请号：US17199315
申请日：2021-03-11
发明人： Charles D. Wait , David Campbell , Jake Truelove , Jody Joyner , Jon K. Kriegel , Glenn O. Kincaid
IPC分类号： G06F12/1009 , G06F12/1045 , G06F12/0864 , G06F12/0882
摘要： A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.
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公开(公告)号：US20220035748A1
公开(公告)日：2022-02-03
申请号：US16941630
申请日：2020-07-29
发明人： David Campbell , Bryan Lloyd , David A. Hrusecky , Kimberly M. Fernsler , Jeffrey A. Stuecheli , Guy L. Guthrie , SAMUEL DAVID KIRCHHOFF , Robert A. Cordes , Michael J. Mack , Brian Chen
IPC分类号： G06F12/1045 , G06F12/0891 , G06F9/30 , G06F9/54
摘要： Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.
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公开(公告)号：US11086787B2
公开(公告)日：2021-08-10
申请号：US16267882
申请日：2019-02-05
发明人： David Campbell , Bryan Lloyd
IPC分类号： G06F12/0877
摘要： A system and method of handling data access demands in a processor virtual cache that includes: determining if a virtual cache data access demand missed because of a difference in the context tag of the data access demand and a corresponding entry in the virtual cache with the same virtual address as the data access demand; in response to the virtual cache missing, determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table.
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公开(公告)号：US20210191866A1
公开(公告)日：2021-06-24
申请号：US17196520
申请日：2021-03-09
发明人： David Campbell , Bryan Lloyd
IPC分类号： G06F12/0815
摘要： A system and method of handling access demands in a virtual cache comprising, by a processing system, checking if a virtual cache access demand missed because of a synonym tagged in the virtual cache; in response to the virtual cache access demand missing because of a synonym tagged in the virtual cache, updating the virtual address tag in the virtual cache to a new virtual address tag; searching for additional synonyms tagged in the virtual cache; and in response to finding additional synonyms tagged in the virtual cache, updating the virtual address tag of the additional synonyms to the new virtual address tag.
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公开(公告)号：US20210049107A1
公开(公告)日：2021-02-18
申请号：US17089324
申请日：2020-11-04
发明人： David Campbell , Dwain A. Hicks
IPC分类号： G06F12/1045 , G06F12/0893 , G06F12/1009
摘要： A computer system includes a translation lookaside buffer (TLB) and a processor. The TLB comprises a first TLB array and a second TLB array, and stores entries comprising virtual address information and corresponding real address information. The processor is configured to receive a first virtual address for translation, and to concurrently determine if the TLB stores a physical address associated with the first virtual address based on a first portion and a second portion of the first virtual address. The first portion is associated with a first page size and the second portion is associated with a second page size (different from the first page size). The first portion is used to perform lookup in either one of the first TLB array and the second TLB array and the second portion is used for performing lookup in other one of the first TLB array and the second TLB array.
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公开(公告)号：US10740248B2
公开(公告)日：2020-08-11
申请号：US16218903
申请日：2018-12-13
发明人： David Campbell , Dwain A. Hicks , Christian Jacobi
IPC分类号： G06F12/10 , G06F12/1036 , G06F12/1018 , G06F12/0862 , G06F9/38 , G06F12/123
摘要： A method or system of translating a virtualized address to a real address is disclosed that includes receiving a virtualized address for translation; generating a predicted intermediate address translation using a portion of the bit field of the virtualized address; determining a predicted real address using the predicted intermediate address or portion thereof; performing a translation of the virtualized address to an actual intermediate address; determining whether the predicted intermediate address is the same as the actual intermediate address; and in response to the predicted intermediate address being the same as the actual intermediate address, providing the predicted real address as the real address.
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