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1.发明授权公开(公告)号：US11243773B1
公开(公告)日：2022-02-08
申请号：US17120371
申请日：2020-12-14
发明人： Bryan Lloyd , David Campbell , Brian Chen , Robert A. Cordes
IPC分类号： G06F9/38
摘要： A computer system, includes a store queue that holds store entries and a load queue that holds load entries sleeping on a store entry. A processor detects a store drain merge operation call and generates a pair of store tags comprising a first store tag corresponding to a first store entry to be drained and a second store tag corresponding to a second store entry to be drained. The processor determines the pair of store tags an even-type store tag or an odd-type store tag. The processor disables the odd store tag included in the even-type store tag pair when detecting the even-type store tag pair, and wakes up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the even-type store tag pair while the odd store tag is disabled.
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公开(公告)号：US10831481B2
公开(公告)日：2020-11-10
申请号：US16433227
申请日：2019-06-06
发明人： Sundeep Chadha , Robert A. Cordes , David A. Hrusecky , Hung Q. Le , Jentje Leenstra , Dung Q. Nguyen , Brian W. Thompto , Albert J. Van Norstrand
IPC分类号： G06F12/0842 , G06F9/30 , G06F12/0813 , G06F12/0875 , G06F12/0862 , G06F9/38 , G06F13/16 , G06F13/42
摘要： Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
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公开(公告)号：US11520704B1
公开(公告)日：2022-12-06
申请号：US17364495
申请日：2021-06-30
发明人： Robert A. Cordes , Bryan Lloyd
IPC分类号： G06F12/0875 , G06F12/0811 , G06F9/30 , G06F12/02 , G06F12/0804
摘要： A load-store unit (LSU) of a processor core determines whether or not a second store operation specifies an adjacent update to that specified by a first store operation. The LSU additionally determines whether the total store data length of the first and second store operations exceeds a maximum size. Based on determining the second store operation specifies an adjacent update and the total store data length does not exceed the maximum size, the LSU merges the first and second store operations and writes merged store data into a same write block of a cache. Based on determining that the total store data length exceeds the maximum size, the LSU splits the second store operation into first and second portions, merges the first portion with the first store operation, and writes store data of the partially merged store operation into the write block.
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公开(公告)号：US10761854B2
公开(公告)日：2020-09-01
申请号：US15132835
申请日：2016-04-19
IPC分类号： G06F9/38
摘要： Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor including receiving a load instruction in a load reorder queue, wherein the load instruction is an instruction to load data from a memory location; subsequent to receiving the load instruction, receiving a store instruction in a store reorder queue, wherein the store instruction is an instruction to store data in the memory location; determining that the store instruction causes a hazard against the load instruction; preventing a flush of the load reorder queue based on a state of the load instruction; and re-executing the load instruction.
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5.发明申请公开(公告)号：US20180121205A1
公开(公告)日：2018-05-03
申请号：US15693387
申请日：2017-08-31
发明人： Maarten J. Boersma , Robert A. Cordes , David A. Hrusecky , Jennifer L. Molnar , Brian W. Thompto , Albert J. Van Norstrand, JR. , Kenneth L. Ward
CPC分类号： G06F9/3855 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/3802 , G06F9/3836 , G06F9/3851 , G06F9/524 , G06F12/0875 , G06F2212/452
摘要： An instruction sequencing unit in an out-of-order (OOO) processor includes a Most Favored Instruction (MFI) mechanism that designates an instruction as an MFI. The processing queues in the processor identify when they contain the MFI, and assures processing the MFI. The MFI remains the MFI until it is completed or is flushed, and which time the MFI mechanism selects the next MFI.
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6.发明授权公开(公告)号：US09940133B2
公开(公告)日：2018-04-10
申请号：US15219638
申请日：2016-07-26
IPC分类号： G06F12/08 , G06F9/30 , G06F12/0875 , G06F12/0811
CPC分类号： G06F9/30043 , G06F9/3834 , G06F9/3891 , G06F12/0811 , G06F12/0817 , G06F12/0875 , G06F2212/283 , G06F2212/452 , G06F2212/621
摘要： Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.
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公开(公告)号：US20220035748A1
公开(公告)日：2022-02-03
申请号：US16941630
申请日：2020-07-29
发明人： David Campbell , Bryan Lloyd , David A. Hrusecky , Kimberly M. Fernsler , Jeffrey A. Stuecheli , Guy L. Guthrie , SAMUEL DAVID KIRCHHOFF , Robert A. Cordes , Michael J. Mack , Brian Chen
IPC分类号： G06F12/1045 , G06F12/0891 , G06F9/30 , G06F9/54
摘要： Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.
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公开(公告)号：US20220019436A1
公开(公告)日：2022-01-20
申请号：US16933241
申请日：2020-07-20
发明人： Bryan Lloyd , Sundeep Chadha , Dung Q. Nguyen , Christian Gerhard Zoellin , Brian W. Thompto , Sheldon Bernard Levenstein , Phillip G. Williams , Robert A. Cordes , Brian Chen
摘要： Provided is a method for fusing store instructions in a microprocessor. The method includes identifying two instructions in an execution pipeline of a microprocessor. The method further includes determining that the two instructions meet a fusion criteria. In response to determining that the two instructions meet the fusion criteria, the two instructions are recoded into a fused instruction. The fused instruction is executed.
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公开(公告)号：US10884742B2
公开(公告)日：2021-01-05
申请号：US16552665
申请日：2019-08-27
发明人： Sundeep Chadha , Robert A. Cordes , David A. Hrusecky , Hung Q. Le , Jentje Leenstra , Dung Q. Nguyen , Brian W. Thompto , Albert J. Van Norstrand, Jr.
IPC分类号： G06F12/0842 , G06F9/30 , G06F12/0813 , G06F12/0875 , G06F12/0862 , G06F9/38 , G06F13/16 , G06F13/42
摘要： Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
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10.发明授权公开(公告)号：US10268518B2
公开(公告)日：2019-04-23
申请号：US15997863
申请日：2018-06-05
IPC分类号： G06F9/46 , G06F9/50 , G06F9/30 , G06F12/0875 , G06F9/38
摘要： Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.
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