公开(公告)号：US20200175122A1

公开(公告)日：2020-06-04

申请号：US16205197

申请日：2018-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gi-Joon Nam ,  David John Geiger ,  Paul G. Villarrubia ,  Shyam Ramji ,  Myung-Chul Kim ,  Benjamin Neil Trombley

IPC: G06F17/50

Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.

公开(公告)号：US20250124201A1

公开(公告)日：2025-04-17

申请号：US18485461

申请日：2023-10-12

Applicant: International Business Machines Corporation

Inventor： Maya Safieddine ,  David John Geiger ,  Ali S. El-Zein ,  Viresh Paruthi

IPC: G06F30/327 ,  G06F30/3323

Abstract: A computer-implemented method for inserting clock-gating in a register-transfer level (RTL) design is provided. The computer-implemented method includes flattening the RTL design, identifying modules and state elements in the RTL design, computing a clock-gating expression for each of the state elements of the RTL design, selecting terms of the clock-gating expression for each one of the state elements that is traceable to signals in a same one of the modules as the one of the state elements, determining which clock-gating terms are equivalent to those of other state elements in the RTL design, clustering state elements with equivalent clock-gating terms into clusters and inserting clock-gating logic, which equates to the equivalent clock-gating terms, into the RTL design for each cluster.

公开(公告)号：US10891411B2

公开(公告)日：2021-01-12

申请号：US16205197

申请日：2018-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gi-Joon Nam ,  David John Geiger ,  Paul G. Villarrubia ,  Shyam Ramji ,  Myung-Chul Kim ,  Benjamin Neil Trombley

IPC: G06F30/327 ,  G06F30/392 ,  G06F111/20

Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.