公开(公告)号：US11080443B2

公开(公告)日：2021-08-03

申请号：US16716683

申请日：2019-12-17

Applicant: International Business Machines Corporation

Inventor： Myung-Chul Kim ,  Arjen Alexander Mets ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Alexander J. Suess ,  Benjamin Trombley ,  Paul G. Villarrubia

IPC: G06F30/327 ,  G06F30/39 ,  G06F30/392 ,  G06F30/3312 ,  G06F30/30 ,  G06F119/12

Abstract: A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

公开(公告)号：US20210117608A1

公开(公告)日：2021-04-22

申请号：US17135260

申请日：2020-12-28

Applicant: International Business Machines Corporation

Inventor： Woohyun Chung ,  Gi-Joon Nam ,  Lakshmi N. Reddy

IPC: G06F30/398 ,  G06F9/44 ,  G06F16/27 ,  G06F30/30 ,  G06F30/33 ,  G06F30/392

Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

公开(公告)号：US20200175122A1

公开(公告)日：2020-06-04

申请号：US16205197

申请日：2018-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gi-Joon Nam ,  David John Geiger ,  Paul G. Villarrubia ,  Shyam Ramji ,  Myung-Chul Kim ,  Benjamin Neil Trombley

IPC: G06F17/50

Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.

公开(公告)号：US20200097833A1

公开(公告)日：2020-03-26

申请号：US16696968

申请日：2019-11-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhou Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

IPC: G06N3/10

Abstract: Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

公开(公告)号：US10552740B2

公开(公告)日：2020-02-04

申请号：US14537844

申请日：2014-11-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhuo Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

IPC: G06N3/10

Abstract: Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

公开(公告)号：US10528695B1

公开(公告)日：2020-01-07

申请号：US16048093

申请日：2018-07-27

Applicant: International Business Machines Corporation

Inventor： Alexey Y. Lvov ,  Gi-Joon Nam ,  Benjamin Neil Trombley ,  Myung-Chul Kim ,  Paul G. Villarrubia

IPC: G06F17/50 ,  G06F17/15

Abstract: A putative circuit design is represented as a set of movable blocks of predetermined size which must fit into a bounding box, with a plurality of subsets to be interconnected by wires. A total weighted wire length is determined as a function of coordinates of centers of the movable blocks by summing a half perimeter wire length over the plurality of subsets, and a density penalty is determined as a convolution of an indicator function of the current placement and a convolution kernel, via incremental integer computation without use of floating point arithmetic. Blocks are moved to minimize a penalty function which is the sum of the total weighted wire length and the product of a density penalty weight and the density penalty. The process repeats until a maximum value of the density penalty weight is reached or the density penalty approaches zero.

公开(公告)号：US10354183B2

公开(公告)日：2019-07-16

申请号：US14537857

申请日：2014-11-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhuo Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

IPC: G06N7/02 ,  G06N7/04 ,  G06N7/06 ,  G06N7/08 ,  G06N3/063 ,  G06F1/3234 ,  G06N3/04

Abstract: Embodiments of the present invention relate to meeting latency constraints in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synthesis under latency constraints is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. Each of the plurality of neurosynaptic cores is modeled as a node in a placement graph. The graph has a plurality of edges. A weight is assigned to each of the plurality of edges based on a spike frequency. An arrangement of the neurosynaptic cores is determined. The arrangement comprises a length of each of the plurality of edges. A maximum length is compared to the length of each of the plurality of edges. The weight of at least one of the plurality of edges is increased where the length is greater than the maximum length.

公开(公告)号：US09536600B2

公开(公告)日：2017-01-03

申请号：US14520403

申请日：2014-10-22

Applicant: International Business Machines Corporation

Inventor： Dongki Kim ,  Jente B. Kuang ,  Janani Mukundan ,  Gi-Joon Nam

IPC: G11C11/56 ,  G11C16/08

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/08

Abstract: Mechanisms are provided, in a non-volatile memory device comprising a non-volatile memory and a memory controller, for controlling an operation of the non-volatile memory device. The non-volatile memory device receives a single combined memory command for accessing the non-volatile memory. The non-volatile memory device decodes the row address and the column address for the word-line to be accessed by the single combined memory command. The non-volatile memory device accesses the word-line such that at least a most significant bit (MSB) page and a least significant bit (LSB) page are accessed simultaneously.

Abstract translation: 在包括用于控制非易失性存储器件的操作的非易失性存储器和存储器控制器的非易失性存储器件中提供了机构。 非易失性存储器装置接收用于访问非易失性存储器的单个组合存储器命令。 非易失性存储器件通过单个组合存储器命令解码要访问的字线的行地址和列地址。 非易失性存储器件访问字线，使得至少最高有效位（MSB）页和最低有效位（LSB）页被同时访问。

公开(公告)号：US20160132767A1

公开(公告)日：2016-05-12

申请号：US14537826

申请日：2014-11-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhuo Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/30

Abstract: Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.

Abstract translation: 本发明的实施例涉及在多核神经突触网络中提供功率最小化。 在本发明的一个实施例中，提供了一种用于电源突触网络合成的方法和计算机程序产品。 神经突触网络的功耗被建模为线长度。 神经突触网络包括多个神经突触核。 通过最小化导线长度来确定突触核心的布置。

公开(公告)号：US20140033154A1

公开(公告)日：2014-01-30

申请号：US14046207

申请日：2013-10-04

Applicant: International Business Machines Corporation

Inventor： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F9/5066

Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

Abstract translation: 区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。 对于少量的移动端口，通过平衡可放置对象来分配计算。 对于每次移动的少量对象，通过平衡移动端口分配计算。 如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。 对于对象平衡，移动端口被分配给一个处理器，直到处理器的摊销对象数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。 对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。 本发明提供多项式时间的时间表，同时保持高质量的结果。