公开(公告)号：US20190279913A1

公开(公告)日：2019-09-12

申请号：US15918077

申请日：2018-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oleg GLUSCHENKOV ,  Zuoguang LIU ,  Shogo MOCHIZUKI ,  Hiroaki NIIMI ,  Tenko YAMASHITA

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/51 ,  H01L29/24 ,  H01L29/161

Abstract: Embodiments of the invention are directed to a method and resulting structures for a complementary metal oxide semiconductor (CMOS) having source and drain contacts formed using trench solid and liquid phase epitaxy (SPE/LPE). In a non-limiting embodiment of the invention, an NFET is formed on a substrate. The NFET includes a p-type semiconductor fin vertically extending from an n-type bottom source or drain region of the substrate. A PFET is also formed on the substrate. The PFET includes an n-type semiconductor fin vertically extending from a p-type bottom source or drain region of the substrate. A first gate is formed over a channel region of the p-type semiconductor fin and a second gate is formed over a channel region of the n-type semiconductor fin. The first gate and the second gate include a common dipole layer. The NFET and PFET each include a linear threshold voltage of about 150 mV to about 250 mV and a difference between the linear threshold voltages of the NFET and PFET is less than about 50 mV.