公开(公告)号：US20180069024A1

公开(公告)日：2018-03-08

申请号：US15795454

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76281 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66583 ,  H01L29/7838 ,  H01L29/7842 ,  H01L29/78684

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US20190279913A1

公开(公告)日：2019-09-12

申请号：US15918077

申请日：2018-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oleg GLUSCHENKOV ,  Zuoguang LIU ,  Shogo MOCHIZUKI ,  Hiroaki NIIMI ,  Tenko YAMASHITA

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/51 ,  H01L29/24 ,  H01L29/161

Abstract: Embodiments of the invention are directed to a method and resulting structures for a complementary metal oxide semiconductor (CMOS) having source and drain contacts formed using trench solid and liquid phase epitaxy (SPE/LPE). In a non-limiting embodiment of the invention, an NFET is formed on a substrate. The NFET includes a p-type semiconductor fin vertically extending from an n-type bottom source or drain region of the substrate. A PFET is also formed on the substrate. The PFET includes an n-type semiconductor fin vertically extending from a p-type bottom source or drain region of the substrate. A first gate is formed over a channel region of the p-type semiconductor fin and a second gate is formed over a channel region of the n-type semiconductor fin. The first gate and the second gate include a common dipole layer. The NFET and PFET each include a linear threshold voltage of about 150 mV to about 250 mV and a difference between the linear threshold voltages of the NFET and PFET is less than about 50 mV.

公开(公告)号：US20210384139A1

公开(公告)日：2021-12-09

申请号：US16891600

申请日：2020-06-03

Applicant: International Business Machines Corporation

Inventor： Huimei ZHOU ,  Su Chen FAN ,  Miaomiao WANG ,  Zuoguang LIU

IPC: H01L23/532 ,  H01L21/768

Abstract: Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

公开(公告)号：US20190019811A1

公开(公告)日：2019-01-17

申请号：US16124291

申请日：2018-09-07

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/285 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US20170186854A1

公开(公告)日：2017-06-29

申请号：US15456650

申请日：2017-03-13

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/161 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76281 ,  H01L21/84 ,  H01L29/66583 ,  H01L29/7838 ,  H01L29/7842 ,  H01L29/78684

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US20170170197A1

公开(公告)日：2017-06-15

申请号：US15266412

申请日：2016-09-15

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/161

CPC classification number: H01L27/1203 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76281 ,  H01L21/84 ,  H01L29/66583 ,  H01L29/7838 ,  H01L29/7842 ,  H01L29/78684

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US20170170195A1

公开(公告)日：2017-06-15

申请号：US14964026

申请日：2015-12-09

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L27/1203 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76281 ,  H01L21/84 ,  H01L29/66583 ,  H01L29/7838 ,  H01L29/7842 ,  H01L29/78684

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.