公开(公告)号：US20040110388A1

公开(公告)日：2004-06-10

申请号：US10314497

申请日：2002-12-06

申请人： International Business Machines Corporation

发明人： Hongwen Yan ,  Brian L. Ji ,  Siddhartha Panda ,  Richard Wise ,  Bomy A. Chen

IPC分类号： H01L021/302 ,  H01L021/461

CPC分类号： H01J37/32623 ,  H01J37/3266

摘要： A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.

摘要翻译： 一种等离子体蚀刻系统，其具有带有磁体的晶片卡盘，该磁体在晶片上施加磁场以将晶片免受带电粒子的影响。 磁场与晶片平行，并且在晶片表面附近最强。 磁场可以是直的或圆形的。 在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，离子被静电排斥偏转。 允许中性物质通过磁场，并且它们与晶片碰撞。 中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。 此外，由于调味过程通常依赖于带电粒子的蚀刻，所以磁场可以保护晶片免受调节过程的调节过程，以便从室表面清洁不需要的膜。

公开(公告)号：US20040150056A1

公开(公告)日：2004-08-05

申请号：US10355726

申请日：2003-01-31

申请人： Infineon Technologies North America Corp ,  International Business Machines Corporation

发明人： Haining Yang ,  Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Rajeev Malik ,  Hongwen Yan ,  Ravikumar Ramachandran

IPC分类号： H01L029/76 ,  H01L029/94

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/76838

摘要： A method of fabricating a semiconductor device having a dielectric structure on which a gate stack having a gate stack surface is formed, the gate stack having one or more gate metal layers comprising a gate metal, wherein the gate metal is recessed from the gate stack surface by a chemical etch, is provided. The method includes oxidizing the gate metal of the gate stack selectively to form a smooth side wall on the gate stack, and depositing a gate spacer to the gate stack.

摘要翻译： 一种制造具有电介质结构的半导体器件的方法，其上形成具有栅叠层表面的栅极叠层，所述栅叠层具有一个或多个包含栅极金属的栅极金属层，其中栅极金属从栅叠层表面凹陷 通过化学蚀刻。 所述方法包括选择性地氧化栅极堆叠的栅极金属，以在栅极堆叠上形成平滑的侧壁，以及将栅极间隔物沉积到栅极叠层。

公开(公告)号：US20030032225A1

公开(公告)日：2003-02-13

申请号：US09928210

申请日：2001-08-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffery Brown ,  Richard Wise ,  Hongwen Yan ,  Qingyun Yang ,  Chienfan Yu

IPC分类号： H01L021/336 ,  H01L021/8234 ,  H01L021/302 ,  H01L021/461

CPC分类号： H01L21/32137 ,  H01L21/28114 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/42376

摘要： A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a SinullC-containing film or combinations thereof.

摘要翻译： 一种用于形成在栅极介电层上具有栅极导体层的缺口栅极结构的方法和结构。 栅极导体层具有第一厚度。 本发明的方法包括在栅极导体层上图案化掩模，在未被掩模保护的区域中将栅极导体层蚀刻到减小的厚度（减小的厚度小于第一厚度），在栅极导体上沉积钝化膜 蚀刻钝化膜以从栅极导体层的水平部分去除钝化膜（使用各向异性蚀刻），选择性地蚀刻栅极导体层以从不受掩模或钝化膜保护的所有区域去除栅极导体层 。 这在栅极导体与栅极介电层相遇的拐角处形成栅极导体层内的底切凹口。 钝化膜包括含C的膜，含Si膜，含Si-C的膜或其组合。

公开(公告)号：US20020132437A1

公开(公告)日：2002-09-19

申请号：US09928212

申请日：2001-08-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Len Y. Tsou ,  Hongwen Yan ,  Qingyun Yang ,  Chienfan Yu

IPC分类号： H01L021/331

CPC分类号： H01L21/28114 ,  H01L29/42376

摘要： A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 nullm electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

摘要翻译： 提供了一种形成具有基本垂直侧壁和小于0.05μm电临界尺寸的缺口门结构的方法。 该方法包括在绝缘层上形成导电层; 在所述导电层上形成掩模，以便至少保护所述导电层的一部分; 各向异性蚀刻未被掩模保护的导电层，以便将导电层变薄到预定厚度并形成掩模下面的导电特征，导电特征具有基本垂直的侧壁; 至少在所述基本垂直的侧壁上形成钝化层; 并且各向同性地蚀刻未被掩模保护的剩余导电层以去除预定厚度，从而暴露不包含钝化层的所述导电特征的下部，同时去除导电特征的下部中的切口区。