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    Vapor phase etch trim structure with top etch blocking layer
    2.
    发明申请
    Vapor phase etch trim structure with top etch blocking layer 失效
    具有顶部蚀刻阻挡层的气相蚀刻修整结构

    公开(公告)号：US20040198030A1

    公开(公告)日：2004-10-07

    申请号：US09989822

    申请日：2001-11-20

    申请人： International Business Machines Corporation

    发明人： Frederick W. Buehrer ,  Derek Chen ,  William Chu ,  Scott Crowder ,  Sadanand V. Deshpande ,  David V. Horak ,  Wesley C. Natzle ,  Hung Y. Ng ,  Len Y. Tsou ,  Chienfan Yu

    IPC分类号： H01L021/3205

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

    摘要： A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.

    摘要翻译： 在具有初始厚度的硬掩模上形成阻挡层。 线通过图案化阻挡层和硬掩模来制造以提供线段，线段具有跨越线段测量的第一尺寸; 使所述线段的表面层反应以在所述线段的剩余部分上形成反应产物层; 并且除去反应产物而不攻击线段的剩余部分，而不攻击阻挡层和基底，以形成跨越比第一尺寸小的线段的具有第二尺寸的线段。 阻挡层防止在硬掩模上形成反应产物，从而保持硬掩模的初始厚度。 阻挡层也可以用作光致抗蚀剂图案化的ARC层，从而不需要使用附加的膜层。

    Method to form gate conductor structures of dual doped polysilicon
    3.
    发明申请
    Method to form gate conductor structures of dual doped polysilicon 有权
    形成双掺杂多晶硅栅极导体结构的方法

    公开(公告)号：US20030186492A1

    公开(公告)日：2003-10-02

    申请号：US10114829

    申请日：2002-04-02

    申请人： International Business Machines Corporation

    发明人： Jeffrey J. Brown ,  Len Y. Tsou ,  Qingyun Yang

    IPC分类号： H01L021/8238

    CPC分类号： H01L21/823842

    摘要： A method for manufacturing a semiconductor chip which has transistors is disclosed. The transistors include first type transistors which have a first type of doping and second type transistors which have a second type of doping different than the first type of doping. The method includes forming a conductive layer on a substrate. The conductive layer includes first regions that have the first type of doping and second regions have the second type of doping. The invention patterns a mask over the conductive layer, and the mask protects portions of the conductive layer where gate conductors will be located. Next, the invention partially etches unprotected portions of the conductive layer. The partially etching process allows a layer of the unprotected portions to remain, such that the substrate is not exposed by the partially etching process. The invention forms a passivating layer on exposed vertical surfaces of the conductive layer and completely etches unprotected portions of the conductive layer to expose the substrate. The invention then dopes exposed portions of the substrate to form source/drain regions.

    摘要翻译： 公开了一种制造具有晶体管的半导体芯片的方法。 晶体管包括具有第一类型掺杂的第一类型晶体管和具有不同于第一类型掺杂的第二类型掺杂的第二类型晶体管。 该方法包括在衬底上形成导电层。 导电层包括具有第一类型的掺杂的第一区域和第二区域具有第二类型的掺杂。 本发明在导电层上形成掩模，并且掩模保护导电层在栅极导体将被定位的部分。 接下来，本发明部分地蚀刻导电层的未受保护的部分。 部分蚀刻工艺允许保留未保护部分的层，使得基板不被部分蚀刻工艺暴露。 本发明在导电层的暴露的垂直表面上形成钝化层，并且完全蚀刻导电层的未受保护的部分以暴露衬底。 然后，本发明掺杂衬底的暴露部分以形成源极/漏极区域。

    Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch
    5.
    发明申请
    Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch 失效
    通过钝化部分蚀刻的栅极侧壁然后使用各向同性蚀刻来制造切口浇口

    公开(公告)号：US20020132437A1

    公开(公告)日：2002-09-19

    申请号：US09928212

    申请日：2001-08-10

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Len Y. Tsou ,  Hongwen Yan ,  Qingyun Yang ,  Chienfan Yu

    IPC分类号： H01L021/331

    CPC分类号： H01L21/28114 ,  H01L29/42376

    摘要： A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 nullm electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

    摘要翻译： 提供了一种形成具有基本垂直侧壁和小于0.05μm电临界尺寸的缺口门结构的方法。 该方法包括在绝缘层上形成导电层; 在所述导电层上形成掩模，以便至少保护所述导电层的一部分; 各向异性蚀刻未被掩模保护的导电层，以便将导电层变薄到预定厚度并形成掩模下面的导电特征，导电特征具有基本垂直的侧壁; 至少在所述基本垂直的侧壁上形成钝化层; 并且各向同性地蚀刻未被掩模保护的剩余导电层以去除预定厚度，从而暴露不包含钝化层的所述导电特征的下部，同时去除导电特征的下部中的切口区。