公开(公告)号：US09292390B2

公开(公告)日：2016-03-22

申请号：US13941969

申请日：2013-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/16 ,  G06F11/14 ,  G06F1/04

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

公开(公告)号：US09009545B2

公开(公告)日：2015-04-14

申请号：US13918587

申请日：2013-06-14

Applicant: International Business Machines Corporation

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/00 ,  G06F11/16

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

Abstract translation: 用于错误恢复的系统和方法包括在硬件电路上的第一周期期间确定多个级的至少一个级中的错误，多个级中的每一级具有主锁存器和影子锁存器。 第一信号被传送到至少一级的输出级，以在第二周期期间使输出级的主锁存器和阴影锁存器停止。 第二信号被传送到至少一级的输入级，以在第二周期期间停止输入级的主锁存器，并且在第三周期期间停止输入级的主锁存器和阴影锁存器。 数据从阴影锁存器恢复到主锁存器，用于至少一个级，并且输入级从错误中恢复。

公开(公告)号：US09715437B2

公开(公告)日：2017-07-25

申请号：US15004602

申请日：2016-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/16 ,  G06F11/14 ,  G06F11/22 ,  G06F1/04 ,  G06F1/10

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

公开(公告)号：US20160140005A1

公开(公告)日：2016-05-19

申请号：US15004602

申请日：2016-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/22

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

Abstract translation: 用于错误恢复的系统和方法包括在硬件电路上的第一周期期间确定多个级的至少一个级中的错误，多个级中的每一级具有主锁存器和影子锁存器。 第一信号被传送到至少一级的输出级，以在第二周期期间使输出级的主锁存器和阴影锁存器停止。 第二信号被传送到至少一级的输入级，以在第二周期期间停止输入级的主锁存器，并且在第三周期期间停止输入级的主锁存器和阴影锁存器。 数据从阴影锁存器恢复到主锁存器，用于至少一个级，并且输入级从错误中恢复。

公开(公告)号：US20150154331A1

公开(公告)日：2015-06-04

申请号：US14616135

申请日：2015-02-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Aditya Bansal ,  Jae-Joon Kim ,  Rahul M. Rao

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G01R31/2881 ,  G01R31/3016 ,  G01R31/31725 ,  G06F17/5068

Abstract: A system for estimating delay deterioration in an integrated circuit includes a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit. A netlist generator generates an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations. A timing analyzer performs a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes.

Abstract translation: 用于估计集成电路中的延迟劣化的系统包括：劣化估计器，用于使用在集成电路的仿真期间监视的电压和逻辑值来估计在集成电路内定义的每个器件的至少一个特性中的每一个寿命的劣化 。 网表生成器为其中每个设备的至少一个设备特性已被修改以反映每个估计的劣化的一个或多个寿命中的每一个产生生命周期结束网表。 定时分析器对每个寿命终端网表执行定时分析，以确定一个或多个寿命中的静态或统计电路路径延迟。

公开(公告)号：US20140372827A1

公开(公告)日：2014-12-18

申请号：US13918587

申请日：2013-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/16

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

Abstract translation: 用于错误恢复的系统和方法包括在硬件电路上的第一周期期间确定多个级的至少一个级中的错误，多个级中的每一级具有主锁存器和影子锁存器。 第一信号被传送到至少一级的输出级，以在第二周期期间使输出级的主锁存器和阴影锁存器停止。 第二信号被传送到至少一级的输入级，以在第二周期期间停止输入级的主锁存器，并且在第三周期期间停止输入级的主锁存器和阴影锁存器。 数据从阴影锁存器恢复到主锁存器，用于至少一个级，并且输入级从错误中恢复。

公开(公告)号：US20140372797A1

公开(公告)日：2014-12-18

申请号：US13941969

申请日：2013-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/14

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.