公开(公告)号：US09087909B2

公开(公告)日：2015-07-21

申请号：US13961003

申请日：2013-08-07

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L23/48

CPC classification number: H01L29/78696 ,  H01L21/3065 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

Abstract translation: 一方面，一种形成电子装置的方法包括以下步骤。 ETSOI晶片的ETSOI层被图案化成一个或多个ETSOI区段，每个ETSOI区段具有约3nm至约20nm的宽度。 在用作晶体管的沟道区的一个或多个ETSOI段的一部分上形成栅电极，其中从栅极下方延伸的一个或多个ETSOI区的部分用作晶体管的源极和漏极区 。 在与晶体管相邻的ETSOI晶片中形成至少一个TSV。 还提供电子设备。

公开(公告)号：US09009545B2

公开(公告)日：2015-04-14

申请号：US13918587

申请日：2013-06-14

Applicant: International Business Machines Corporation

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/00 ,  G06F11/16

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

Abstract translation: 用于错误恢复的系统和方法包括在硬件电路上的第一周期期间确定多个级的至少一个级中的错误，多个级中的每一级具有主锁存器和影子锁存器。 第一信号被传送到至少一级的输出级，以在第二周期期间使输出级的主锁存器和阴影锁存器停止。 第二信号被传送到至少一级的输入级，以在第二周期期间停止输入级的主锁存器，并且在第三周期期间停止输入级的主锁存器和阴影锁存器。 数据从阴影锁存器恢复到主锁存器，用于至少一个级，并且输入级从错误中恢复。

公开(公告)号：US09653615B2

公开(公告)日：2017-05-16

申请号：US13800124

申请日：2013-03-13

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L23/48 ,  H01L21/84

CPC classification number: H01L29/78696 ,  H01L21/3065 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

公开(公告)号：US09292390B2

公开(公告)日：2016-03-22

申请号：US13941969

申请日：2013-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/16 ,  G06F11/14 ,  G06F1/04

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

公开(公告)号：US20140264605A1

公开(公告)日：2014-09-18

申请号：US13961003

申请日：2013-08-07

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L23/48 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L21/3065 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

公开(公告)号：US10083880B2

公开(公告)日：2018-09-25

申请号：US15494992

申请日：2017-04-24

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L21/3065 ,  H01L23/48 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

公开(公告)号：US20140264593A1

公开(公告)日：2014-09-18

申请号：US13800124

申请日：2013-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/3065 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

Abstract translation: 一方面，一种形成电子装置的方法包括以下步骤。 ETSOI晶片的ETSOI层被图案化成一个或多个ETSOI区段，每个ETSOI区段具有约3nm至约20nm的宽度。 在用作晶体管的沟道区的一个或多个ETSOI段的一部分上形成栅电极，其中从栅极下方延伸的一个或多个ETSOI区的部分用作晶体管的源极和漏极区 。 在与晶体管相邻的ETSOI晶片中形成至少一个TSV。 还提供电子设备。

公开(公告)号：US20170229353A1

公开(公告)日：2017-08-10

申请号：US15494992

申请日：2017-04-24

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L21/84 ,  H01L29/786 ,  H01L21/768 ,  H01L23/48 ,  H01L27/12 ,  H01L21/3065

CPC classification number: H01L29/78696 ,  H01L21/3065 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

公开(公告)号：US20140372827A1

公开(公告)日：2014-12-18

申请号：US13918587

申请日：2013-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/16

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

Abstract translation: 用于错误恢复的系统和方法包括在硬件电路上的第一周期期间确定多个级的至少一个级中的错误，多个级中的每一级具有主锁存器和影子锁存器。 第一信号被传送到至少一级的输出级，以在第二周期期间使输出级的主锁存器和阴影锁存器停止。 第二信号被传送到至少一级的输入级，以在第二周期期间停止输入级的主锁存器，并且在第三周期期间停止输入级的主锁存器和阴影锁存器。 数据从阴影锁存器恢复到主锁存器，用于至少一个级，并且输入级从错误中恢复。

公开(公告)号：US20140372797A1

公开(公告)日：2014-12-18

申请号：US13941969

申请日：2013-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jae-Joon Kim ,  Yu-Shiang Lin ,  Insup Shin

IPC: G06F11/14

CPC classification number: G06F11/2215 ,  G06F1/04 ,  G06F1/10 ,  G06F11/1402 ,  G06F11/1407 ,  G06F11/1415 ,  G06F11/1604 ,  G06F11/1608

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.