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    Clock buffers with pulse drive capability for power efficiency
    3.
    发明授权
    Clock buffers with pulse drive capability for power efficiency 有权
    具有脉冲驱动能力的时钟缓冲器，实现功率效率

    公开(公告)号：US09571100B2

    公开(公告)日：2017-02-14

    申请号：US14973363

    申请日：2015-12-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Aditya Bansal ,  Thomas J. Bucelot ,  Alan J. Drake ,  Phillip J. Restle ,  David W. Shan ,  Mrigank Sharad

    IPC: G06F1/04 ,  H03K19/00 ,  H03K3/012 ,  H03K5/05 ,  H03K5/13 ,  H03K5/06 ,  H03K5/135 ,  H03K5/00

    CPC classification number: H03K19/0016 ,  H03K3/012 ,  H03K5/05 ,  H03K5/06 ,  H03K5/13 ,  H03K5/135 ,  H03K2005/00013 ,  H03K2005/00234

    Abstract: A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.

    Abstract translation: 提供时钟驱动程序。 时钟驱动器包括具有输入，正脉冲驱动分支，负脉冲驱动分支和输出的多级延迟单元。 该输入用于接收输入到时钟驱动器的参考时钟信号的原始版本，并用于产生全局时钟信号。 输出连接到正脉冲驱动分支和负脉冲驱动分支。 时钟驱动器还包括脉冲发生器，其具有分别连接到正和负脉冲驱动分支的输出的正和负脉冲发生器部分。 脉冲发生器在任何给定时间产生响应于正脉冲使能信号和负脉冲使能信号的正脉冲和负脉冲之一，以及输入到时钟驱动器的参考时钟信号的原始版本，而没有 修改。

    Clock buffers with pulse drive capability for power efficiency
    4.
    发明授权
    Clock buffers with pulse drive capability for power efficiency 有权
    具有脉冲驱动能力的时钟缓冲器，实现功率效率

    公开(公告)号：US09276563B2

    公开(公告)日：2016-03-01

    申请号：US14303671

    申请日：2014-06-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Aditya Bansal ,  Thomas J. Bucelot ,  Alan J. Drake ,  Phillip J. Restle ,  David W. Shan ,  Mrigank Sharad

    IPC: G06F1/04 ,  H03K3/012 ,  H03K5/05 ,  H03K5/13 ,  H03K5/00

    CPC classification number: H03K19/0016 ,  H03K3/012 ,  H03K5/05 ,  H03K5/06 ,  H03K5/13 ,  H03K5/135 ,  H03K2005/00013 ,  H03K2005/00234

    Abstract: A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.

    Abstract translation: 提供了时钟驱动器和相应的方法。 时钟驱动器包括具有逻辑电路和多个串行连接的延迟元件的多级延迟单元。 延迟元件的输入接收输入到时钟驱动器的参考时钟信号的原始版本，并用于产生全局时钟信号。 延迟元件的输出连接到由逻辑电路形成的正和负脉冲驱动分支。 时钟驱动器还包括形成正和负脉冲发生器部分的脉冲发生器，分别连接到正和负脉冲驱动分支的输出。 脉冲发生器在任何给定时间产生响应于正脉冲使能信号和负脉冲使能信号的正脉冲和负脉冲之一，以及输入到时钟驱动器的参考时钟信号的原始版本，而没有 修改。

    CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS
    5.
    发明申请
    CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS 审中-公开
    电路技术，用于电气特征块封装

    公开(公告)号：US20150179536A1

    公开(公告)日：2015-06-25

    申请号：US14634820

    申请日：2015-02-28

    Applicant: International Business Machines Corporation

    Inventor： Emrah Acar ,  Aditya Bansal ,  Dureseti Chidambarrao ,  Liang-Teck Pang ,  Amith Singhee

    IPC: H01L21/66 ,  H01L27/02 ,  H01L27/11

    CPC classification number: H01L22/34 ,  H01L22/14 ,  H01L27/0203 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

    Abstract translation: 物理测试集成电路具有对应于集成电路设计的多个重复电路部分。 这些部分中的第一部分被制造成具有标称块掩模位置，并且附加的部分被有意地用块掩模位置与标称块掩模位置的预定逐渐增加的偏移来制造。 对于每个部分，确定第一场效应晶体管和第二场效应晶体管之间的阈值电压差。 块掩模位置的预定逐渐增加的偏移在从第一场效应晶体管到第二场效应晶体管的方向上。 在与零差异的阈值电压的差的变化相对应的逐行增加偏移的值处确定块掩模覆盖公差。 还公开了用于片上监视的方法和相应的电路。

    ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS
    6.
    发明申请
    ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS 审中-公开
    在集成电路中设备降级估计延迟检测

    公开(公告)号：US20150154331A1

    公开(公告)日：2015-06-04

    申请号：US14616135

    申请日：2015-02-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Aditya Bansal ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G01R31/2881 ,  G01R31/3016 ,  G01R31/31725 ,  G06F17/5068

    Abstract: A system for estimating delay deterioration in an integrated circuit includes a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit. A netlist generator generates an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations. A timing analyzer performs a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes.

    Abstract translation: 用于估计集成电路中的延迟劣化的系统包括：劣化估计器，用于使用在集成电路的仿真期间监视的电压和逻辑值来估计在集成电路内定义的每个器件的至少一个特性中的每一个寿命的劣化 。 网表生成器为其中每个设备的至少一个设备特性已被修改以反映每个估计的劣化的一个或多个寿命中的每一个产生生命周期结束网表。 定时分析器对每个寿命终端网表执行定时分析，以确定一个或多个寿命中的静态或统计电路路径延迟。

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