公开(公告)号：US09105677B2

公开(公告)日：2015-08-11

申请号：US14059531

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu ,  James S. Nakos

IPC: H01L29/732 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66242 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

Abstract translation: 根据本文中具有晶体管顶部和晶体管底部的双极晶体管结构，位于晶体管底部的硅衬底具有第一导电类型的集电极区域。 相对于晶体管顶部和底部，第二导电类型的外延基底层覆盖集电极区域的一部分。 外延基底层在硅衬底上具有底表面和与底表面相对的顶表面。 外延基底层相对于晶体管顶部和底部的顶部区域包含具有足以避免影响晶体管参数并且足以抵抗选择性化学蚀刻的原子组成的锗浓度。 第一导电类型的硅发射极层相对于晶体管顶部和底部覆盖与外延基底层的顶表面相邻的外延基底层的一部分。

公开(公告)号：US20150108548A1

公开(公告)日：2015-04-23

申请号：US14059531

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu ,  James S. Nakos

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66242 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

Abstract translation: 根据本文中具有晶体管顶部和晶体管底部的双极晶体管结构，位于晶体管底部的硅衬底具有第一导电类型的集电极区域。 相对于晶体管顶部和底部，第二导电类型的外延基底层覆盖集电极区域的一部分。 外延基底层在硅衬底上具有底表面和与底表面相对的顶表面。 外延基底层相对于晶体管顶部和底部的顶部区域包含具有足以避免影响晶体管参数并且足以抵抗选择性化学蚀刻的原子组成的锗浓度。 第一导电类型的硅发射极层相对于晶体管顶部和底部覆盖与外延基底层的顶表面相邻的外延基底层的一部分。

公开(公告)号：US20150357295A1

公开(公告)日：2015-12-10

申请号：US14830816

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/66 ,  H01L29/06 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

公开(公告)号：US20150303275A1

公开(公告)日：2015-10-22

申请号：US14755862

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu ,  James S. Nakos

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

CPC classification number: H01L29/66242 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

公开(公告)号：US20140061727A1

公开(公告)日：2014-03-06

申请号：US14073178

申请日：2013-11-06

Applicant: International Business Machines Corporation

Inventor： Renata A. Camillo-Castillo ,  James S. Dunn ,  David L. Harame ,  Anthony K. Stamper

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/737

Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.

Abstract translation: 形成集成电路结构的方法包括：通过延伸通过浅沟槽隔离（STI）形成通气孔并进入衬底; 在所述通气孔的底部选择性地去除所述衬底的暴露部分以在所述衬底内形成开口，其中所述衬底内的所述开口邻接所述STI的底表面或侧壁中的至少一个; 并密封通气孔以在基底内的开口中形成气隙。

公开(公告)号：US09653477B2

公开(公告)日：2017-05-16

申请号：US14147186

申请日：2014-01-03

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  James S. Dunn ,  Blaine J. Gross ,  Qizhi Liu ,  James A. Slinkman

IPC: H01L21/336 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/45 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L27/1203 ,  H01L21/3081 ,  H01L21/764 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7842

Abstract: Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.

公开(公告)号：US09355972B2

公开(公告)日：2016-05-31

申请号：US14196137

申请日：2014-03-04

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/66 ,  H01L49/02 ,  H01L29/06 ,  H01L23/522 ,  H01L21/762

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Abstract translation: 在混合信号集成电路（IC）的体硅（Si）衬底中制造电介质区域的结构和方法提供了高Q无源谐振器。 通过湿法蚀刻在<100>方向内的本体Si衬底内的深沟槽扩大以形成连续的空腔，其由Si氧化物填充以形成电介质区域。 电介质区域增强了在混合信号IC的金属化层中形成的覆盖无源谐振器的质量（Q）。

公开(公告)号：US09269787B2

公开(公告)日：2016-02-23

申请号：US14755862

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu ,  James S. Nakos

IPC: H01L21/8222 ,  H01L29/66 ,  H01L29/08 ,  H01L21/762 ,  H01L29/06 ,  H01L29/165 ,  H01L29/732

CPC classification number: H01L29/66242 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

公开(公告)号：US20150364492A1

公开(公告)日：2015-12-17

申请号：US14834696

申请日：2015-08-25

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  James S. Dunn ,  Blaine J. Gross ,  Qizhi Liu ,  James A. Slinkman

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/165 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/3081 ,  H01L21/764 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7842

Abstract: Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

Abstract translation: 各种实施例包括场效应晶体管（FET）和相关的集成电路（IC）布局。 一个FET包括：包括一组沟槽的硅衬底; 邻接硅衬底的第一氧化物; 覆盖硅衬底的硅锗（SiGe）层; 覆盖SiGe层的硅层; 覆盖硅层的第二氧化物，其中硅层包括多个硅化物区域; 覆盖相邻自对准硅化物区域之间的第二氧化物的栅极结构; 以及接触所述栅极结构的第一接触; 接触一个所述自对准区域的第二接触点; 部分地填充该组沟槽并在覆盖SiGe层的硅层上方延伸的第三氧化物; 以及在所述一组沟槽中的每一个中的气隙，所述气隙由所述第三氧化物包围。

公开(公告)号：US08872305B2

公开(公告)日：2014-10-28

申请号：US14073178

申请日：2013-11-06

Applicant: International Business Machines Corporation

Inventor： Renata A. Camillo-Castillo ,  James S. Dunn ,  David L. Harame ,  Anthony K. Stamper

IPC: H01L29/737 ,  H01L21/764 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/737

Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.

Abstract translation: 形成集成电路结构的方法包括：通过延伸通过浅沟槽隔离（STI）形成通气孔并进入衬底; 在所述通气孔的底部选择性地去除所述衬底的暴露部分以在所述衬底内形成开口，其中所述衬底内的所述开口邻接所述STI的底表面或侧壁中的至少一个; 并密封通气孔以在基底内的开口中形成气隙。