公开(公告)号：US10133581B2

公开(公告)日：2018-11-20

申请号：US14595549

申请日：2015-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey Carl Brownscheidle ,  Sundeep Chadha ,  Maureen Anne Delaney ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/30 ,  G06F9/38

摘要： An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

公开(公告)号：US20160202990A1

公开(公告)日：2016-07-14

申请号：US14595549

申请日：2015-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey Carl Brownscheidle ,  Sundeep Chadha ,  Maureen Anne Delaney ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F9/3891

摘要： An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

摘要翻译： 用于处理器核的执行片电路具有多个并行指令执行片，并且提供内部资源的灵活且有效的使用。 执行切片电路包括用于接收第一指令流的指令的主执行片和用于接收第二指令流的指令的从属执行片和需要大于片的宽度的执行宽度的第一指令流的指令。 执行切片电路还包括控制逻辑，该控制逻辑检测第一指令流的第一指令何时具有更大的宽度，并且控制从执行切片以保留第一发行周期，用于并行跨主主执行切片发出第一指令， 从属执行片。

公开(公告)号：US20160202992A1

公开(公告)日：2016-07-14

申请号：US14724073

申请日：2015-05-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey Carl Brownscheidle ,  Sundeep Chadha ,  Maureen Anne Delaney ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F9/3891

摘要： A method of processing using an execution slice circuit including multiple parallel instruction execution slices provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The method also detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

摘要翻译： 使用包括多个并行指令执行片的执行片电路的处理方法提供内部资源的灵活且有效的使用。 执行切片电路包括用于接收第一指令流的指令的主执行片和用于接收第二指令流的指令的从属执行片和需要大于片的宽度的执行宽度的第一指令流的指令。 该方法还检测第一指令流的第一指令何时具有更大的宽度并且控制从执行片保留用于在主执行片和从执行片并行地发出第一指令的第一发行周期。

公开(公告)号：US10223125B2

公开(公告)日：2019-03-05

申请号：US16048946

申请日：2018-07-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey Carl Brownscheidle ,  Sundeep Chadha ,  Maureen Anne Delaney ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30

摘要： An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

公开(公告)号：US20180336038A1

公开(公告)日：2018-11-22

申请号：US16048946

申请日：2018-07-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey Carl Brownscheidle ,  Sundeep Chadha ,  Maureen Anne Delaney ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F9/3891

摘要： An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.