公开(公告)号：US20160202988A1

公开(公告)日：2016-07-14

申请号：US14724268

申请日：2015-05-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/08

CPC分类号： G06F9/3802 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/608

摘要： A method of operation of a processor core execution unit circuit provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

摘要翻译： 处理器核心执行单元电路的操作方法通过减少加载存储单元发行队列的每入口存储要求来提供区域和能量的有效使用。 执行单元电路包括再循环队列，其存储加载和存储操作的有效地址以及由存储操作存储的值。 队列控制逻辑控制再循环队列并发出队列，使得在已经计算了加载或存储操作的有效地址之后，将加载操作或存储操作的有效地址写入循环队列并且移除操作 从问题队列中，使发送队列条目中的地址操作数和其他值不再需要存储。 当加载或存储操作被缓存单元拒绝时，其随后从再循环队列重新发行。

公开(公告)号：US20160202986A1

公开(公告)日：2016-07-14

申请号：US14595635

申请日：2015-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/608

摘要： An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

摘要翻译： 在处理器核心中使用的执行单元电路通过减少加载存储单元发出队列的每个入口存储要求来提供区域和能量的有效使用。 执行单元电路包括再循环队列，其存储加载和存储操作的有效地址以及由存储操作存储的值。 队列控制逻辑控制再循环队列并发出队列，使得在已经计算了加载或存储操作的有效地址之后，将加载操作或存储操作的有效地址写入循环队列并且移除操作 从问题队列中，使发送队列条目中的地址操作数和其他值不再需要存储。 当加载或存储操作被缓存单元拒绝时，其随后从再循环队列重新发行。

公开(公告)号：US20230273793A1

公开(公告)日：2023-08-31

申请号：US18312380

申请日：2023-05-04

申请人： International Business Machines Corporation

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC分类号： G06F9/3802 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3885 ,  G06F9/3836 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/608

摘要： An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

公开(公告)号：US20210406023A1

公开(公告)日：2021-12-30

申请号：US17467882

申请日：2021-09-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875

摘要： An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

公开(公告)号：US10133581B2

公开(公告)日：2018-11-20

申请号：US14595549

申请日：2015-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey Carl Brownscheidle ,  Sundeep Chadha ,  Maureen Anne Delaney ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/30 ,  G06F9/38

摘要： An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

公开(公告)号：US10133576B2

公开(公告)日：2018-11-20

申请号：US14595635

申请日：2015-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875

摘要： An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

公开(公告)号：US20160202990A1

公开(公告)日：2016-07-14

申请号：US14595549

申请日：2015-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey Carl Brownscheidle ,  Sundeep Chadha ,  Maureen Anne Delaney ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F9/3891

摘要： An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

摘要翻译： 用于处理器核的执行片电路具有多个并行指令执行片，并且提供内部资源的灵活且有效的使用。 执行切片电路包括用于接收第一指令流的指令的主执行片和用于接收第二指令流的指令的从属执行片和需要大于片的宽度的执行宽度的第一指令流的指令。 执行切片电路还包括控制逻辑，该控制逻辑检测第一指令流的第一指令何时具有更大的宽度，并且控制从执行切片以保留第一发行周期，用于并行跨主主执行切片发出第一指令， 从属执行片。

公开(公告)号：US12061909B2

公开(公告)日：2024-08-13

申请号：US18312380

申请日：2023-05-04

申请人： International Business Machines Corporation

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC分类号： G06F9/3802 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/608

摘要： An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

公开(公告)号：US11150907B2

公开(公告)日：2021-10-19

申请号：US16049038

申请日：2018-07-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875

摘要： An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

公开(公告)号：US20160202992A1

公开(公告)日：2016-07-14

申请号：US14724073

申请日：2015-05-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey Carl Brownscheidle ,  Sundeep Chadha ,  Maureen Anne Delaney ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F9/3891

摘要： A method of processing using an execution slice circuit including multiple parallel instruction execution slices provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The method also detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

摘要翻译： 使用包括多个并行指令执行片的执行片电路的处理方法提供内部资源的灵活且有效的使用。 执行切片电路包括用于接收第一指令流的指令的主执行片和用于接收第二指令流的指令的从属执行片和需要大于片的宽度的执行宽度的第一指令流的指令。 该方法还检测第一指令流的第一指令何时具有更大的宽度并且控制从执行片保留用于在主执行片和从执行片并行地发出第一指令的第一发行周期。