公开(公告)号：US10083039B2

公开(公告)日：2018-09-25

申请号：US15883601

申请日：2018-01-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0846

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0848 ,  G06F12/0875 ,  G06F2212/1048 ,  G06F2212/282 ,  G06F2212/452 ,  H05K999/99 ,  Y02D10/13

摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.

公开(公告)号：US20160202986A1

公开(公告)日：2016-07-14

申请号：US14595635

申请日：2015-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/608

摘要： An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

摘要翻译： 在处理器核心中使用的执行单元电路通过减少加载存储单元发出队列的每个入口存储要求来提供区域和能量的有效使用。 执行单元电路包括再循环队列，其存储加载和存储操作的有效地址以及由存储操作存储的值。 队列控制逻辑控制再循环队列并发出队列，使得在已经计算了加载或存储操作的有效地址之后，将加载操作或存储操作的有效地址写入循环队列并且移除操作 从问题队列中，使发送队列条目中的地址操作数和其他值不再需要存储。 当加载或存储操作被缓存单元拒绝时，其随后从再循环队列重新发行。

公开(公告)号：US20150324206A1

公开(公告)日：2015-11-12

申请号：US14300563

申请日：2014-06-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, JR.

IPC分类号： G06F9/38

CPC分类号： G06F9/38 ,  G06F9/30149 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3873 ,  G06F9/3887 ,  G06F9/4881 ,  G06F9/505 ,  G06F9/5066 ,  G06F9/5083

摘要： A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

摘要翻译： 具有多个并行指令执行片并且耦合到由调度路由网络耦合的多个调度队列的处理器核心的操作方法提供了内部资源的灵活和有效的使用。 根据指令流的执行要求和指令执行片中的资源的可用性，控制调度路由网络动态地改变片和指令流之间的关系。 可以在单指令多数据（SIMD）指令执行和基于每个指令的普通指令执行之间动态地重新配置指令执行片。 具有大于单个指令执行片段的宽度的操作数宽度的指令可以被配置为为特定指令一致地起作用的多个指令执行片段来处理。 当指令执行片正忙于处理其中一个流的当前指令时，可以选择另一个片段来继续执行。

公开(公告)号：US20180150300A1

公开(公告)日：2018-05-31

申请号：US15883601

申请日：2018-01-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, JR.

IPC分类号： G06F9/38 ,  G06F12/0875 ,  G06F12/0846 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0848 ,  G06F12/0875 ,  G06F2212/1048 ,  G06F2212/282 ,  G06F2212/452

摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.

公开(公告)号：US09971602B2

公开(公告)日：2018-05-15

申请号：US14723940

申请日：2015-05-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0846 ,  G06F12/0875

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0848 ,  G06F12/0875 ,  G06F2212/1048 ,  G06F2212/282 ,  G06F2212/452

摘要： A method of operating a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.

公开(公告)号：US20160202989A1

公开(公告)日：2016-07-14

申请号：US14594716

申请日：2015-01-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, JR.

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0848 ,  G06F12/0875 ,  G06F2212/1048 ,  G06F2212/282 ,  G06F2212/452

摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.

摘要翻译： 具有多个并行指令执行片并通过调度路由网络耦合到多个调度队列的处理器核心提供内部资源的灵活和有效的使用。 执行片的配置是可选择的，使得可以根据指令流的执行要求来调整处理器核的能力。 根据一个或多个也用作配置控制信号的模式控制信号，可以将两个或更多个执行片组合成超片以处理较宽的数据，较宽的操作数和/或矢量操作。 模式控制信号还用于根据是否选择单线程或多线程操作以及另外根据活动的多个硬件线程来分配处理器核心内的执行片段的簇。

公开(公告)号：US20160202988A1

公开(公告)日：2016-07-14

申请号：US14724268

申请日：2015-05-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/08

CPC分类号： G06F9/3802 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/608

摘要： A method of operation of a processor core execution unit circuit provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

摘要翻译： 处理器核心执行单元电路的操作方法通过减少加载存储单元发行队列的每入口存储要求来提供区域和能量的有效使用。 执行单元电路包括再循环队列，其存储加载和存储操作的有效地址以及由存储操作存储的值。 队列控制逻辑控制再循环队列并发出队列，使得在已经计算了加载或存储操作的有效地址之后，将加载操作或存储操作的有效地址写入循环队列并且移除操作 从问题队列中，使发送队列条目中的地址操作数和其他值不再需要存储。 当加载或存储操作被缓存单元拒绝时，其随后从再循环队列重新发行。

公开(公告)号：US20150324204A1

公开(公告)日：2015-11-12

申请号：US14274927

申请日：2014-05-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Lee Evan Eisen ,  Hung Qui Le ,  Jentje Leenstra ,  Jose Eduardo Moreira ,  Bruce Joseph Ronchetti ,  Brian William Thompto ,  Albert James Van Norstrand, JR.

IPC分类号： G06F9/38

CPC分类号： G06F9/38 ,  G06F9/30149 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3873 ,  G06F9/3887 ,  G06F9/4881 ,  G06F9/505 ,  G06F9/5066 ,  G06F9/5083

摘要： A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis, permitting the mixture of those instruction types. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

摘要翻译： 具有多个并行指令执行片并通过调度路由网络耦合到多个调度队列的处理器核心提供内部资源的灵活和有效的使用。 根据指令流的执行要求和指令执行片中的资源的可用性，控制调度路由网络动态地改变片和指令流之间的关系。 可以在单指令多数据（SIMD）指令执行和基于每个指令的普通指令执行之间动态地重新配置指令执行片，允许这些指令类型的混合。 具有大于单个指令执行片段的宽度的操作数宽度的指令可以被配置为为特定指令一致地起作用的多个指令执行片段来处理。 当指令执行片正忙于处理其中一个流的当前指令时，可以选择另一个片段来继续执行。

公开(公告)号：US11734010B2

公开(公告)日：2023-08-22

申请号：US17467882

申请日：2021-09-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC分类号： G06F9/3802 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/608

摘要： An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

公开(公告)号：US10223125B2

公开(公告)日：2019-03-05

申请号：US16048946

申请日：2018-07-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jeffrey Carl Brownscheidle ,  Sundeep Chadha ,  Maureen Anne Delaney ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC分类号： G06F9/38 ,  G06F9/30

摘要： An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.