公开(公告)号：US20150242560A1

公开(公告)日：2015-08-27

申请号：US14190723

申请日：2014-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  Jeanne P. BICKFORD ,  Mark W. KUEMERLE

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

Abstract: Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.

Abstract translation: 提供的方法和系统被设计为施加n型到p型装置偏斜约束，该约束超出正常技术限制允许以在较低电压下操作半导体器件，同时仍然在较低功率下实现类似的性能。 更具体地，提供了一种方法，其包括：针对至少一个库元素设置设备偏斜要求，基于设置的设备偏差要求来设置用于至少一个库元素的设备偏斜测试配置，使用设备来设计至少一个库元素 在产品上制造包括至少一个设备偏斜监视器的至少一个库元件，使用至少一个设备偏斜监视器确定所制造的至少一个库元件的实际设备偏差，以及确定所制造的产品 达到目标规格。

公开(公告)号：US20160364516A1

公开(公告)日：2016-12-15

申请号：US14734411

申请日：2015-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  Mark W. KUEMERLE ,  Qing LI

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5077 ,  G06F2217/06 ,  G06F2217/66 ,  G06F2217/84

Abstract: A computing device for a generating composite view for an intellectual property (IP) core may obtain constraints for multiple application specific integrated circuits (ASIC) designs in which the IP core is used; and determine composite constraints for the IP core based on the constraints for the multiple ASIC designs. The composite constraints may be within all constraints for the multiple ASIC designs. A freedom of change to update the particular IP core may be identified based on the composite constraints.

Abstract translation: 用于知识产权（IP）核心的生成复合视图的计算设备可以获得其中使用IP核的多个专用集成电路（ASIC）设计的约束; 并基于多个ASIC设计的约束来确定IP核的复合约束。 复合约束可以在多个ASIC设计的所有约束内。 可以基于复合约束来识别更新特定IP核的自由。