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公开(公告)号：US20170094808A1
公开(公告)日：2017-03-30
申请号：US14941908
申请日：2015-11-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： William L. BRODSKY , Silvio DRAGONE , Roger S. KRABBENHOFT , David C. LONG , Stefano S. OGGIONI , Michael T. PEETS , William SANTIAGO-FERNANDEZ
CPC classification number: G01D5/16 , H05K1/0275 , H05K1/0298 , H05K1/182 , H05K3/30 , H05K3/32 , H05K2201/09263 , H05K2201/096 , H05K2201/10151 , H05K2201/10371
Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.
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公开(公告)号：US20190049269A1
公开(公告)日：2019-02-14
申请号：US16162679
申请日：2018-10-17
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： William L. BRODSKY , Silvio DRAGONE , Roger S. KRABBENHOFT , David C. LONG , Stefano S. OGGIONI , Michael T. PEETS , William SANTIAGO-FERNANDEZ
CPC classification number: G01D5/16 , H05K1/0275 , H05K1/0298 , H05K1/182 , H05K3/30 , H05K3/32 , H05K2201/09263 , H05K2201/096 , H05K2201/10151 , H05K2201/10371
Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.
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公开(公告)号：US20190017844A1
公开(公告)日：2019-01-17
申请号：US16136589
申请日：2018-09-20
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： William L. BRODSKY , Silvio DRAGONE , Roger S. KRABBENHOFT , David C. LONG , Stefano S. OGGIONI , Michael T. PEETS , William SANTIAGO-FERNANDEZ
CPC classification number: G01D5/16 , H05K1/0275 , H05K1/0298 , H05K1/182 , H05K3/30 , H05K3/32 , H05K2201/09263 , H05K2201/096 , H05K2201/10151 , H05K2201/10371
Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.
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公开(公告)号：US20170089729A1
公开(公告)日：2017-03-30
申请号：US14865610
申请日：2015-09-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： William L. BRODSKY , Silvio DRAGONE , Roger S. KRABBENHOFT , David C. LONG , Stefano S. OGGIONI , Michael T. PEETS , William SANTIAGO-FERNANDEZ
CPC classification number: G01D5/16 , H05K1/0275 , H05K1/0298 , H05K1/182 , H05K3/30 , H05K3/32 , H05K2201/09263 , H05K2201/096 , H05K2201/10151 , H05K2201/10371
Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.
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