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公开(公告)号：US11037650B2
公开(公告)日：2021-06-15
申请号：US16774505
申请日：2020-01-28
Applicant: International Business Machines Corporation
Inventor： Alper Buyuktosunoglu , Swagath Venkataramani , Rajiv Joshi , Karthik V. Swaminathan , Schuyler Eldridge , Pradip Bose
Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.
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2.发明申请公开(公告)号：US20200241954A1
公开(公告)日：2020-07-30
申请号：US16262832
申请日：2019-01-30
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Swagath Venkataramani , Schuyler Eldridge , Karthik V. Swaminathan , Alper Buyuktosunoglu , Pradip Bose
Abstract: A coarse error correction system for detecting, predicting, and correcting errors in neural networks is provided. The coarse error correction system receives a first set of statistics that are computed from values collected from a neural network during a training phase of the neural network. The coarse error correction system computes a second set of statistics based on values collected from the neural network during a run-time phase of the neural network. The coarse error correction system detects an error in the neural network during the run-time phase of the neural network by comparing the first set of statistics with the second set of statistics. The coarse error correction system increases a voltage setting to the neural network based on the detected error.
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3.发明授权公开(公告)号：US11002791B2
公开(公告)日：2021-05-11
申请号：US16874059
申请日：2020-05-14
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Alper Buyuktosunoglu , Schuyler Eldridge , Karthik V. Swaminathan , Yazhou Zu
IPC: G01R31/3183 , G01R31/317 , G06F30/00
Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.
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4.发明申请公开(公告)号：US20200300913A1
公开(公告)日：2020-09-24
申请号：US16874059
申请日：2020-05-14
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Alper Buyuktosunoglu , Schuyler Eldridge , Karthik V. Swaminathan , Yazhou Zu
IPC: G01R31/3183 , G01R31/317 , G06F30/00
Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.
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5.发明申请公开(公告)号：US20200158782A1
公开(公告)日：2020-05-21
申请号：US16398972
申请日：2019-04-30
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Alper Buyuktosunoglu , Schuyler Eldridge , Karthik V. Swaminathan , Yazhou Zu
IPC: G01R31/3183 , G01R31/317 , G06F30/00
Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11630152B2
公开(公告)日：2023-04-18
申请号：US17192164
申请日：2021-03-04
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Alper Buyuktosunoglu , Schuyler Eldridge , Karthik V. Swaminathan , Yazhou Zu
IPC: G01R31/3183 , G01R31/317 , G06F30/00
Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.
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公开(公告)号：US20200168290A1
公开(公告)日：2020-05-28
申请号：US16774505
申请日：2020-01-28
Applicant: International Business Machines Corporation
Inventor： Alper Buyuktosunoglu , Swagath Venkataramani , Rajiv Joshi , Karthik V. Swaminathan , Schuyler Eldridge , Pradip Bose
Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.
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8.发明申请公开(公告)号：US20190164048A1
公开(公告)日：2019-05-30
申请号：US15825660
申请日：2017-11-29
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Alper Buyuktosunoglu , Schuyler Eldridge , Karthik V. Swaminathan , Swagath Venkataramani
Abstract: A system includes a determination component that determines output for successively larger neural networks of a set; and a consensus component that determines consensus between a first neural network and a second neural network of the set. A linear chain of increasingly complex neural networks trained on progressively larger inputs is utilized (e.g., increasingly complex neural networks is generally representative of increased accuracy). Outputs of progressively networks are computed until a consensus point is reached—where two or more successive large networks yield a same inference output. At such point of consensus the larger neural network of the set reaching consensus can be deemed appropriately sized (or of sufficient complexity) for a classification task at hand.
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9.发明申请公开(公告)号：US20210270897A1
公开(公告)日：2021-09-02
申请号：US17192164
申请日：2021-03-04
Applicant: International Business Machines Corporation
Inventor： Pradip Bose , Alper Buyuktosunoglu , Schuyler Eldridge , Karthik V. Swaminathan , Yazhou Zu
IPC: G01R31/3183 , G01R31/317 , G06F30/00
Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.
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10.发明授权公开(公告)号：US11016840B2
公开(公告)日：2021-05-25
申请号：US16262832
申请日：2019-01-30
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Swagath Venkataramani , Schuyler Eldridge , Karthik V. Swaminathan , Alper Buyuktosunoglu , Pradip Bose
Abstract: A coarse error correction system for detecting, predicting, and correcting errors in neural networks is provided. The coarse error correction system receives a first set of statistics that are computed from values collected from a neural network during a training phase of the neural network. The coarse error correction system computes a second set of statistics based on values collected from the neural network during a run-time phase of the neural network. The coarse error correction system detects an error in the neural network during the run-time phase of the neural network by comparing the first set of statistics with the second set of statistics. The coarse error correction system increases a voltage setting to the neural network based on the detected error.
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