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公开(公告)号:US20230178429A1
公开(公告)日:2023-06-08
申请号:US17643408
申请日:2021-12-08
发明人: TSUNG-SHENG KANG , RUILONG XIE , TAO LI , CHIH-CHAO YANG
IPC分类号: H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/3213
CPC分类号: H01L21/76879 , H01L21/32136 , H01L21/32139 , H01L21/76837 , H01L21/76852 , H01L21/76885 , H01L23/5226 , H01L23/5283 , H01L23/53252
摘要: A method of manufacturing an interconnect structure for a semiconductor device is provided. The method includes forming a metal interconnect layer on a substrate. The method includes forming a hardmask on the metal interconnect layer, patterning the metal interconnect layer and hardmask, forming a sacrificial material layer to overfill the patterned metal interconnect layer and hardmask, and selectively removing a portion of the sacrificial layer and the hardmask to form a via opening. The method also includes forming a via on the metal interconnect layer in the via opening by a selective metal growth process.