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    DIELECTRIC CAP LAYER FOR REPLACEMENT GATE WITH SELF-ALIGNED CONTACT
    5.
    发明申请
    DIELECTRIC CAP LAYER FOR REPLACEMENT GATE WITH SELF-ALIGNED CONTACT 审中-公开
    具有自对准接触的替换门的电介质层

    公开(公告)号：US20140134836A1

    公开(公告)日：2014-05-15

    申请号：US13672864

    申请日：2012-11-09

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

    发明人： BALASUBRAMANIAN PRANATHARTHIHARAN ,  CHARAN VEERA VENKATA SATYA SURISETTY ,  JUNLI WANG ,  CHANG SEO PARK ,  RUILONG XIE

    IPC分类号： H01L21/283

    CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

    摘要： Embodiments of the present invention provide a method of forming borderless contact for transistors. The method includes forming a sacrificial gate structure embedded in a first dielectric layer, the sacrificial gate structure including a sacrificial gate and a second dielectric layer surrounding a top and sidewalls of the sacrificial gate; removing a portion of the second dielectric layer that is above a top level of the sacrificial gate to create a first opening surrounded directly by the first dielectric layer; removing the sacrificial gate exposed by the removing of the portion of the second dielectric layer to create a second opening surrounded by a remaining portion of the second dielectric layer; filling the second opening with one or more conductive materials to form a gate of a transistor; and filling the first opening with a layer of dielectric material to form a dielectric cap of the gate of the transistor.

    摘要翻译： 本发明的实施例提供了一种形成晶体管的无边界接触的方法。 该方法包括形成嵌入在第一介电层中的牺牲栅极结构，所述牺牲栅极结构包括牺牲栅极和围绕所述牺牲栅极的顶部和侧壁的第二介电层; 去除位于所述牺牲栅极顶层之上的所述第二电介质层的一部分以产生由所述第一介电层直接包围的第一开口; 去除通过去除第二介电层的部分而暴露的牺牲栅极，以产生由第二介电层的剩余部分包围的第二开口; 用一种或多种导电材料填充第二开口以形成晶体管的栅极; 以及用一层介电材料填充第一开口以形成晶体管的栅极的电介质盖。

    FORMING CROSSBAR AND NON-CROSSBAR TRANSISTORS ON THE SAME SUBSTRATE
    7.
    发明申请
    FORMING CROSSBAR AND NON-CROSSBAR TRANSISTORS ON THE SAME SUBSTRATE 有权

    公开(公告)号：US20220367700A1

    公开(公告)日：2022-11-17

    申请号：US17316832

    申请日：2021-05-11

    申请人： International Business Machines Corporation

    发明人： INDIRA SESHADRI ,  ARDASHEIR RAHMAN ,  RUILONG XIE ,  HEMANTH JAGANNATHAN

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8238

    摘要： A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

    PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE
    8.
    发明申请
    PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE 有权
    集成电路制造工艺，包括均匀深度浸渍技术

    公开(公告)号：US20170012105A1

    公开(公告)日：2017-01-12

    申请号：US15273777

    申请日：2016-09-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

    发明人： QING LIU ,  RUILONG XIE ,  CHUN-CHEN YEH

    IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49

    CPC分类号： H01L29/42376 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

    摘要： Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

    摘要翻译： 从预金属层去除虚拟门以产生具有第一长度的第一开口和第二开口（具有长于第一长度的第二长度）。 用于金属栅电极的功函数金属设置在第一和第二开口中。 沉积钨以填充第一开口并保形地排列第二开口，从而留下第三个开口。 钨层的厚度基本上等于第一开口的长度。 第三个开口填充绝缘材料。 然后使用干蚀刻将钨从第一和第二开口凹入到与金属前层的顶表面基本相同的深度以完成金属栅电极。 然后在凹槽操作之后留下的开口填充有在包括金属栅电极的栅堆叠上形成盖的电介质材料。