公开(公告)号：US20210103821A1

公开(公告)日：2021-04-08

申请号：US16596716

申请日：2019-10-08

Applicant: International Business Machines Corporation

Inventor： TAYFUN GOKMEN

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04

Abstract: Machine learning is enhanced by efficiently updating a weight that is represented as a conductivity of a resistive processing unit (RPU) that is connected between a row wire and a column wire. The weight is updated by the RPU interacting with bit streams carried on the row and column wires. Efficiency of the update is enhanced by calculating a bit length for the bit streams as a function of factors that include learning rate η, maximum activity xmax, maximum error differential δmax, and minimum weight update increment Δwmin.

公开(公告)号：US20220019877A1

公开(公告)日：2022-01-20

申请号：US16929172

申请日：2020-07-15

Applicant: International Business Machines Corporation

Inventor： SEYOUNG KIM ,  Oguzhan Murat Onen ,  TAYFUN GOKMEN ,  MALTE JOHANNES RASCH

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F9/30 ,  G06K9/62

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating analog crossbar arrays. The embodiments include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a first bit-length to represent the number, wherein the bit-length is a modifiable bit length. The embodiments also include selecting pulse positions in a pulse sequence having the first bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

公开(公告)号：US20220019876A1

公开(公告)日：2022-01-20

申请号：US16929168

申请日：2020-07-15

Applicant: International Business Machines Corporation

Inventor： SEYOUNG KIM ,  Oguzhan Murat Onen ,  TAYFUN GOKMEN ,  MALTE JOHANNES RASCH

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F9/30

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating an analog crossbar array. Embodiment include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a bit-length to represent the number. Embodiments also include selecting pulse positions in a pulse sequence having the bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

公开(公告)号：US20230185874A1

公开(公告)日：2023-06-15

申请号：US17551326

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： TAYFUN GOKMEN

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Techniques facilitating automatic non-linearity correction for analog hardware are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an adjustment component that determines a non-linear correction term for an output of an array of analog memories based on a result of a matrix vector multiplication performed on the array of analog memories. The computer executable components can also comprise a rectification component that applies the non-linear correction term to additional outputs of the array of analog memories.

公开(公告)号：US20210279556A1

公开(公告)日：2021-09-09

申请号：US16808811

申请日：2020-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： TAYFUN GOKMEN ,  SEYOUNG KIM ,  MURAT ONEN

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/08

Abstract: Aspects of the invention include a first matrix resistive processing unit (“RPU”) array receives a first input vector along the rows of the first matrix RPU. A second matrix RPU array receives a second input vector along the rows of the second matrix RPU. A reference matrix RPU array receives an inverse of the first input vector along the rows of the reference matrix RPU and an inverse of the second input vector along the rows of the reference matrix RPU. A plurality of analog to digital converters are coupled to respective outputs of a plurality of summing junctions that receive respective column outputs of the first matrix RPU array, the second matrix RPU array, and the reference RPU array and provides a digital value of the output of the plurality of summing junctions.

公开(公告)号：US20210142153A1

公开(公告)日：2021-05-13

申请号：US16676639

申请日：2019-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： TAYFUN GOKMEN ,  Abdullah Kayi

IPC: G06N3/063 ,  G06F15/80 ,  G06F13/36 ,  G06N3/04 ,  G06N3/08

Abstract: Embodiments are directed to forming and training a resistive processing unit (RPU) system. The RPU system is formed from a plurality of RPU tiles, whereby the RPU tiles are the atomic building block of the RPU system. The plurality of RPU tiles is configured as a plurality of RPU chips. The plurality of RPU compute nodes is formed from the plurality of RPU chips. The plurality of RPU compute nodes can further be connected by a low latency, high speed network. The RPU system is trained for an artificial neural network model using the atomic matrix operations of a forward cycle, backward cycle, and matrix update.