公开(公告)号：US20210279556A1

公开(公告)日：2021-09-09

申请号：US16808811

申请日：2020-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： TAYFUN GOKMEN ,  SEYOUNG KIM ,  MURAT ONEN

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/08

Abstract: Aspects of the invention include a first matrix resistive processing unit (“RPU”) array receives a first input vector along the rows of the first matrix RPU. A second matrix RPU array receives a second input vector along the rows of the second matrix RPU. A reference matrix RPU array receives an inverse of the first input vector along the rows of the reference matrix RPU and an inverse of the second input vector along the rows of the reference matrix RPU. A plurality of analog to digital converters are coupled to respective outputs of a plurality of summing junctions that receive respective column outputs of the first matrix RPU array, the second matrix RPU array, and the reference RPU array and provides a digital value of the output of the plurality of summing junctions.

公开(公告)号：US20210264247A1

公开(公告)日：2021-08-26

申请号：US16797587

申请日：2020-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： MINGU KANG ,  KYU-HYOUN KIM ,  SEYOUNG KIM ,  CHIA-YU CHEN

IPC: G06N3/08 ,  G06N3/04

Abstract: A computer-implemented method for improving the efficiency of computing an activation function in a neural network system includes initializing, by a controller, weights in a weight vector associated with the neural network system. Further, the method includes receiving, by the controller, an input vector of input values for computing a dot product with the weight vector for the activation function, which determines an output value of a node in the neural network system. The method further includes predicting, by a rectifier linear unit (ReLU), which computes the activation function, that the output value of the node will be negative based on computing an intermediate value for computing the dot product, and based on a magnitude of the intermediate value exceeding a precomputed threshold value. Further, the method includes, in response to the prediction, terminating, by the ReLU, the computation of the dot product, and outputting a 0 as the output value.

公开(公告)号：US20200050929A1

公开(公告)日：2020-02-13

申请号：US16100673

申请日：2018-08-10

Applicant: International Business Machines Corporation

Inventor： Effendi Leobandung ,  Zhibin Ren ,  SEYOUNG KIM ,  Paul Michael Solomon

IPC: G06N3/063 ,  G06N3/04

Abstract: Method, systems, crosspoint arrays, and systems for tuning a neural network. A crosspoint array includes: a set of conductive rows, a set of conductive columns intersecting the set of conductive rows to form a plurality of crosspoints, a circuit element coupled to each of the plurality of crosspoints configured to store a weight of the neural network, a voltage source associated with each conductive row, a first integrator attached at the end of at least one of the conductive column, and a first variable resistor attached to the integrator and the end of the at least one conductive column.

公开(公告)号：US20220019877A1

公开(公告)日：2022-01-20

申请号：US16929172

申请日：2020-07-15

Applicant: International Business Machines Corporation

Inventor： SEYOUNG KIM ,  Oguzhan Murat Onen ,  TAYFUN GOKMEN ,  MALTE JOHANNES RASCH

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F9/30 ,  G06K9/62

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating analog crossbar arrays. The embodiments include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a first bit-length to represent the number, wherein the bit-length is a modifiable bit length. The embodiments also include selecting pulse positions in a pulse sequence having the first bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

公开(公告)号：US20220019876A1

公开(公告)日：2022-01-20

申请号：US16929168

申请日：2020-07-15

Applicant: International Business Machines Corporation

Inventor： SEYOUNG KIM ,  Oguzhan Murat Onen ,  TAYFUN GOKMEN ,  MALTE JOHANNES RASCH

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F9/30

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating an analog crossbar array. Embodiment include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a bit-length to represent the number. Embodiments also include selecting pulse positions in a pulse sequence having the bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

公开(公告)号：US20190165128A1

公开(公告)日：2019-05-30

申请号：US16100317

申请日：2018-08-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： SEYOUNG KIM ,  CHOONGHYUN LEE ,  INJO OK ,  SOON-CHEON SEO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/737 ,  H01L29/732 ,  H01L21/324 ,  H01L21/308 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/66242 ,  H01L21/02112 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/324 ,  H01L29/0684 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7378 ,  H01L2924/1305

Abstract: A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins. An emitter, a base and a collector contacts are formed to connect to the second semiconductor pattern, the silicon germanium pattern and the first semiconductor layer, respectively. The BJT structures manufactured are also provided.