公开(公告)号：US20240114807A1

公开(公告)日：2024-04-04

申请号：US17936982

申请日：2022-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Victor W.C. Chan ,  JIN PING HAN ,  Samuel Sung Shik Choi ,  Injo Ok

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1286 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683 ,  H01L45/1691

Abstract: An integrated circuit includes a field effect transistor (FET) and a phase change memory (PCM) cell. The PCM cell includes a heater, wherein a bottom surface of the heater is at or below a top surface of the FET.

公开(公告)号：US20200083117A1

公开(公告)日：2020-03-12

申请号：US16684616

申请日：2019-11-15

Applicant: International Business Machines Corporation

Inventor： Andrew Greene ,  Victor W.C. Chan ,  GANGADHARA RAJA MUTHINTI

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/532 ,  H01L21/28 ,  H01L23/522

Abstract: A technique relates to a semiconductor device. One or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates are formed. Source and drain (S/D) contacts are formed, at least one material of the S/D contacts being formed in the PFET gates. Insulating material is deposited as self-aligned caps above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts. Middle of the line (MOL) contacts are formed above the S/D contacts.

公开(公告)号：US20180061754A1

公开(公告)日：2018-03-01

申请号：US15800154

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Victor W.C. Chan ,  Xuefeng Liu ,  Yann A. M. Mignot ,  Yongan Xu

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/28247 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5283

Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.