RECEIVING APPARATUS CAPABLE OF REMOVING INTERFERENCE SIGNAL AND METHOD THEREOF
    1.
    发明申请
    RECEIVING APPARATUS CAPABLE OF REMOVING INTERFERENCE SIGNAL AND METHOD THEREOF 审中-公开
    接收装置可以消除干扰信号及其方法

    公开(公告)号:US20080317180A1

    公开(公告)日:2008-12-25

    申请号:US12013130

    申请日:2008-01-11

    CPC classification number: H04B1/12

    Abstract: An apparatus and method capable of interference signal removal is provided. The receiving apparatus includes a signal reception unit, a sampler which samples signal with carrier wave frequency, a signal filter, and a signal combiner.

    Abstract translation: 提供了能够干扰信号去除的装置和方法。 该接收装置包括:信号接收单元,用载波频率采样信号的采样器,信号滤波器和信号组合器。

    HIGH RESOLUTION TIME DETECTING APPARATUS USING INTERPOLATION AND TIME DETECTING METHOD USING THE SAME
    2.
    发明申请
    HIGH RESOLUTION TIME DETECTING APPARATUS USING INTERPOLATION AND TIME DETECTING METHOD USING THE SAME 有权
    使用插值和时间检测方法的高分辨率时间检测装置

    公开(公告)号:US20090027088A1

    公开(公告)日:2009-01-29

    申请号:US11935424

    申请日:2007-11-06

    CPC classification number: H03D13/00 H03L7/091 H03L2207/50

    Abstract: A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size.

    Abstract translation: 提供了使用内插的高分辨率时间检测装置和使用其的时间检测方法。 时间检测装置包括:延迟器,其通过使用多个延迟元件顺序延迟参考信号来产生延迟信号;锁存单元,其使用延迟信号输出锁存信号;以及内插单元,其使用输入和输出信号输出内插信号 延迟元素。 结果,使用内插的高分辨率TDC和使用其的时间检测方法提供了数字PLL,低功耗的高分辨率数字信号输出和受控电路尺寸的改进的性能。

    DIGITAL FREQUENCY DETECTOR AND DIGITAL PHASE LOCKED LOOP USING THE DIGITAL FREQUENCY DETECTOR
    4.
    发明申请
    DIGITAL FREQUENCY DETECTOR AND DIGITAL PHASE LOCKED LOOP USING THE DIGITAL FREQUENCY DETECTOR 有权
    使用数字频率检测器的数字频率检测器和数字相位锁定环路

    公开(公告)号:US20080315921A1

    公开(公告)日:2008-12-25

    申请号:US11971654

    申请日:2008-01-09

    CPC classification number: H03D13/003 H03L7/091

    Abstract: A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

    Abstract translation: 提供数字频率检测器和数字锁相环(PLL)。 数字频率检测器包括:第一转换单元,其使用在第一频率的高电平周期中工作的第一环形振荡器将第一频率作为数字类型的第一频率信息输出;第二转换单元,输出第二频率作为 使用在第二频率的高电平时段中工作的第二环形振荡器的数字类型的第二频率信息,以及通过计算第一频率信息与第二频率的比率来输出第一频率的数字频率的操作单元 频率信息。

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