公开(公告)号：US20230334117A1

公开(公告)日：2023-10-19

申请号：US18111033

申请日：2023-02-17

Applicant: Imagination Technologies Limited

Inventor： Thomas Ferrere

IPC: G06F17/16 ,  G06F7/483

CPC classification number: G06F17/16 ,  G06F7/483

Abstract: A method of performing dot product of an array of ‘2k’ floating point numbers comprising two sets of k floating-point numbers ai and bi is disclosed. The method includes receiving both sets of ‘k’ floating point numbers and multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of ‘r’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of ‘n’ bits. Further the method includes identifying a maximum exponent sum (emax) among k exponent sums (eabi) of each pair of floating point numbers ai and bi, aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) and adding the set of ‘k’ numbers concurrently to obtain the dot product.

公开(公告)号：US20210294949A1

公开(公告)日：2021-09-23

申请号：US17207030

申请日：2021-03-19

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

公开(公告)号：US20240037303A1

公开(公告)日：2024-02-01

申请号：US18377746

申请日：2023-10-06

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/33

CPC classification number: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

公开(公告)号：US20230333812A1

公开(公告)日：2023-10-19

申请号：US18111178

申请日：2023-02-17

Applicant: Imagination Technologies Limited

Inventor： Thomas Ferrere

IPC: G06F7/487 ,  G06F17/16

CPC classification number: G06F7/4876 ,  G06F17/16

Abstract: A method of performing dot product of an array of ‘2k’ floating point numbers comprising two sets of k floating-point numbers ai and bi is disclosed. The method includes receiving both sets of ‘k’ floating point numbers and multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of ‘r+log (k−1)+1’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of ‘n’ bits. Further the method includes identifying a maximum exponent sum (emax) among k exponent sums (eabi) of each pair of floating point numbers ai and bi aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) and adding the set of ‘k’ numbers concurrently to obtain the dot product.

公开(公告)号：US11783105B2

公开(公告)日：2023-10-10

申请号：US17207030

申请日：2021-03-19

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/30 ,  G06F30/33

CPC classification number: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.