公开(公告)号：US20170075658A1

公开(公告)日：2017-03-16

申请号：US15262168

申请日：2016-09-12

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

Abstract translation: 方法和领先的零预测器，用于估计固定点算术运算结果中的前导零数，这对任何带符号的固定点数都精确到一位以内。 前置零预测器包括输入编码电路，其从固定点数生成编码输入串; 基于窗口的代理串生成电路，其生成代数串，其前导码是通过检查编码输入串的连续窗口并设置代理串的相应位的算术运算结果中的前导码的估计值， 考试; 以及计数器电路，被配置为基于所述替代串中的前一个来估计所述算术运算结果中的前导零的数目。

公开(公告)号：US20160335055A1

公开(公告)日：2016-11-17

申请号：US15218306

申请日：2016-07-25

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane

IPC: G06F7/74 ,  G06F9/30

CPC classification number: G06F7/74 ,  G06F9/30029

Abstract: A trailing/leading zero counter includes a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block includes two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also include one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

公开(公告)号：US09424030B2

公开(公告)日：2016-08-23

申请号：US14598459

申请日：2015-01-16

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane

IPC: G06F7/00 ,  G06F9/30 ,  G06F7/74

CPC classification number: G06F7/74 ,  G06F9/30029

Abstract: A trailing/leading zero counter includes a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block includes two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also include one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

Abstract translation: 尾部/前导零计数器包括多个硬件逻辑块，每个硬件逻辑块计算输出值的一个位（即，尾随/前导零的数量，取决于它是否是尾部/前导零计数器）。 每个硬件逻辑块包括两个部分硬件逻辑块，每个块部分接收输入串的一部分并从该部分的位产生一个或两个输出。 组合逻辑然后组合部分硬件逻辑的输出以生成输出值的位。 对于计算除输出的最低有效位之外的位的硬件逻辑块，硬件逻辑块还包括一个或多个OR还原级，通过使用OR门的比特组合来减少输入串的长度，所得到的字符串是 分为两部分，并输入到硬件逻辑部分。

公开(公告)号：US20230305812A1

公开(公告)日：2023-09-28

申请号：US18204872

申请日：2023-06-01

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US10346137B2

公开(公告)日：2019-07-09

申请号：US16152021

申请日：2018-10-04

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US20180067727A1

公开(公告)日：2018-03-08

申请号：US15810081

申请日：2017-11-12

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane

IPC: G06F7/74 ,  G06F9/30

CPC classification number: G06F7/74 ,  G06F9/30029

Abstract: A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also comprise one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

公开(公告)号：US20170147289A1

公开(公告)日：2017-05-25

申请号：US15426907

申请日：2017-02-07

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane

IPC: G06F7/74 ,  G06F9/30

CPC classification number: G06F7/74 ,  G06F9/30029

Abstract: A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also comprise one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

公开(公告)号：US11669305B2

公开(公告)日：2023-06-06

申请号：US17187120

申请日：2021-02-26

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US20210182028A1

公开(公告)日：2021-06-17

申请号：US17187120

申请日：2021-02-26

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US20190034171A1

公开(公告)日：2019-01-31

申请号：US16152021

申请日：2018-10-04

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.